YOKOGAWA TA220 User Manual page 59

Explanation
IM 704610-01E
You can choose to turn the PLL hold function, D-to-C high speed calculation, AGC
circuit, or DC clamp function ON or OFF.
PLL Hold
The PLL hold function maintains the frequency of the clock signal regenerated in the PLL
circuit when Inhibit is active. If RF signals whose clock signals cannot be regenerated in
the PLL circuit are input to the measurement input terminal when Inhibit is active, once
Inhibit is cleared, if a normal RF signal whose clock signal can be regenerated in the PLL
circuit is then introduced, the clock signal will be generated normally. With PLL hold
turned ON, when Inhibit is turned ON and an inhibit signal is input, the PLL hold function
activates at the same time.
D-to-C High Speed Calculation
You can update the measured D-to-C jitter values every 2 ms. The measured values of
the measurement clock delimited every 2 ms is moving-summed over the gate time
range, and the results are updated every 2 ms. The D-to-C high speed calculation
function is not available on products with suffix code -BDS.
AGC
If undulations occur in the signal amplitude envelope, the signal can be applied to the
AGC circuit to normalize the fluctuations in the amplitude.
DC Clamp
If RF signals with temporarily changing DC components are applied to the measurement
input terminal when Inhibit is active, the DC clamp function can be used to quickly
attenuate the changed portion of the DC components. The changed portion of the DC
component is immediately attenuated, and regeneration of the clock signal by the PLL
circuit is maintained. With DC clamp turned ON, when Inhibit is turned ON and an inhibit
signal is input, the DC clamp function activates at the same time.
Note
When the limit equalizer is selected (see the option function user's manual, IM704610-51E),
the PLLhold and DCclamp functions are not available. The limit equalizer cannot be selected
as an option for products with suffix code -BDS.
4.9 Other Functions
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