YOKOGAWA TA220 User Manual page 29

2.4 Measurement Conditions
PLL Hold <<For procedures, see section 4.9>>
D-to-C High Speed Calculation <For the setup procedure, see section 4.9>
AGC (Automatic Gain Control Amplifier) <<For procedures, see section 4.9>>
DC Clamp <<For procedures, see section 4.9>>
2-12
The PLL hold function maintains the frequency of the clock signal regenerated in the PLL
circuit when Inhibit is active. If RF signals whose clock signals cannot be regenerated in
the PLL circuit are input to the measurement input terminal when Inhibit is active, once
Inhibit is cleared, if a normal RF signal whose clock signal can be regenerated in the PLL
circuit is then introduced, the clock signal will be generated normally.
With normal D-to-C jitter measurement, when this function is enabled the measured D-
to-C jitter is updated every 2 ms rather than being updated according to a specified gate
time. For example, if the gate time is set to 8 ms, the measured values of the
measurement clock delimited every 2 ms as in the figure below is moving-summed over
an 8-ms time range, and the results are updated every 2 ms.
The D-to-C high speed calculation function is not available on products with suffix code -
BDS.
Gate time of 8 ms
2 ms 2 ms 2 ms 2 ms
Outputs the moving-summed result every 2 ms.
The summing time is the same as the gate time.
If undulations occur in the signal amplitude envelope, the signal can be applied to an
AGC circuit to normalize the fluctuations in the amplitude thereby improving the accuracy
of jitter measurements.
If RF signals with temporarily changing DC components are applied to the measurement
input terminal when Inhibit is active, the DC clamp function can be used to quickly
attenuate the changed portion of the DC components. The low-band cutoff frequency in
the equalizer circuit is changed from 10 kHz to 3 MHz, the changed portion of the DC
component is immediately attenuated, and regeneration of the clock signal by the PLL
circuit is maintained.
Gate time of 8 ms
2 ms 2 ms 2 ms 2 ms
Gate time of 8 ms
2 ms 2 ms
IM 704610-01E