Input/Output Ports; Pull-High Resistors - Holtek BS86DH12C Manual

BS86DH12C
High Voltage Touch A/D Flash MCU with HVIO

Input/Output Ports

Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
This device provides bidirectional input/output lines. These I/O ports are mapped to the RAM Data
Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these
I/O ports can be used for input and output operations. For input operation, these ports are non-
latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]",
where "m" denotes the port address. For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Register
Name
7
PA PA7
PAC PAC7
PAPU PAPU7
PAWU PAWU7
PB PB7
PBC PBC7
PBPU PBPU7
PC —
PCC —
PCPU —

Pull-high Resistors

Many product applications require pull-high resistors for their switch inputs usually requiring
the use of an external resistor. To eliminate the need for these external resistors, all I/O pins,
when configured as a digital input have the capability of being connected to an internal pull-high
resistor. These pull-high resistors are selected using the relevant pull-high control registers and are
implemented using weak PMOS transistors.
Note that the pull-high resistor can be controlled by the relevant pull-high control register only when
the pin-shared functional pin is selected as a digital input or NMOS output. Otherwise, the pull-high
resistors cannot be enabled.
• PxPU Register
Bit 7
Name PxPU7
R/W R/W
POR 0
PxPUn: I/O Port x Pin pull-high function control
0: Disable
1: Enable
The PxPUn bit is used to control the pin pull-high function. Here the "x" is the Port name
which can be A, B or C. However, the actual available bits for each I/O Port may be
different.
Rev. 1.00
Bit
6 5 4
PA6 PA5 PA4
PAC6 PAC5 PAC4
PAPU6 PAPU5 PAPU4
PAWU6 PAWU5 PAWU4
PB6 PB5 PB4
PBC6 PBC5 PBC4
PBPU6 PBPU5 PBPU4
— PC5 PC4
— PCC5 PCC4
— PCPU5 PCPU4
I/O Logic Function Register List
6 5 4
PxPU6 PxPU5 PxPU4
R/W R/W R/W
0 0 0
63
3 2 1
PA3 PA2 PA1
PAC3 PAC2 PAC1
PAPU3 PAPU2 PAPU1
PAWU3 PAWU2 PAWU1
PB3 PB2 PB1
PBC3 PBC2 PBC1
PBPU3 PBPU2 PBPU1
PC3 PC2 PC1
PCC3 PCC2 PCC1
PCPU3 PCPU2 PCPU1
"—": Unimplemented, read as "0"
3 2 1
PxPU3 PxPU2 PxPU1
R/W R/W R/W
0 0 0
October 26, 2018
0
PA0
PAC0
PAPU0
PAWU0
PB0
PBC0
PBPU0
PC0
PCC0
PCPU0
0
PxPU0
R/W
0