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Holtek BS83B24C Manual

Touch flash mcu
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Touch Flash MCU
BS83B24C/BS83C40C
Revision: V1.00
Date: �e���a�� 0�� �01�
�e���a�� 0�� �01�

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  • Page 1: Ope�Ating

    Touch Flash MCU BS83B24C/BS83C40C Revision: V1.00 Date: �e���a�� 0�� �01� �e���a�� 0�� �01�...

  • Page 2: Table Of Contents

    BS83B24C/BS83C40C Touch Flash MCU Table of Contents Features ......................6 CPU �eat��es ......................... 6 Pe�iphe�al �eat��es ......................... 6 General Description ..................7 Selection Table ....................7 Block Diagram ....................8 Pin Assignment ....................8 Pin Description ....................9 Absolute Maximum Ratings ................17 D.C.
  • Page 3 BS83B24C/BS83C40C Touch Flash MCU Special Function Register Description ............35 Indi�ect Add�essing Registe�s – IAR0� IAR1� IAR� ............... 35 Memo�� Pointe�s – MP0� MP1L� MP1H� MP�L� MP�H ............35 Acc�m�lato� – ACC ......................36 P�og�am Co�nte� Low Registe� – PCL ................. 3�...
  • Page 4 BS83B24C/BS83C40C Touch Flash MCU Timer Modules – TM ..................76 Int�od�ction ........................... �6 TM Ope�ation ........................�6 TM Clock So��ce ........................�6 TM Inte���pts ......................... �� TM Exte�nal Pins ........................�� P�og�amming Conside�ations ....................�� Compact Type TM – CTM ................79 Compact TM Ope�ation ......................

  • Page 5: I/O Pin St

    BS83B24C/BS83C40C Touch Flash MCU A�ithmetic Ope�ations ......................16� Logical and Rotate Ope�ation ..................... 163 B�anches and Cont�ol T�ansfe� ................... 163 Bit Ope�ations ........................163 Ta�le Read Ope�ations ....................... 163 Othe� Ope�ations ......................... 163 Instruction Set Summary ................164 Ta�le Conventions ....................... 164 Extended Inst��ction Set .....................

  • Page 6: Features

    BS83B24C/BS83C40C Touch Flash MCU Features CPU Features • Operating Voltage =8MHz: 2.2V~5.5V ♦ =12MHz: 2.7V~5.5V ♦ =16MHz: 3.3V~5.5V ♦ • Up to 0.25μs instruction cycle with 16MHz system clock at V • Power down and wake-up functions to reduce power consumption • Oscillator types: Internal High Speed 8/12/16MHz RC Oscillator – HIRC ♦ Internal Low Speed 32kHz RC Oscillator– LIRC ♦ External Low Speed 32.768kHz Crystal – LXT ♦ • Fully integrated internal oscillators require no external components • Multi-mode operation: FAST, SLOW, IDLE and SLEEP • All instructions executed in 1~3 instruction cycles • Table read instructions • 115 powerful instructions • 6-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: Up to 4K×16...

  • Page 7: General Description

    BS83B24C/BS83C40C Touch Flash MCU General Description The series of devices are the Flash Memory 8-bit high performance RISC architecture microcontrollers with fully integrated touch key functions. With the touch key function provided internally and with the convenience of Flash Memory multi-programming features, this series of devices have all the features to offer designer a reliable and easy means of implementing touch keys with their product applications. The Touch key function is completely integrated eliminating the need for external components. In addition to the Flash program memory, other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Protective features such as an internal Watchdog Timer and Low Voltage Reset coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of external, internal high and low oscillator functions are provided including fully integrated system oscillators which require no external components for their implementation. The...

  • Page 8: Block Diagram

    BS83B24C/BS83C40C Touch Flash MCU Block Diagram 4K × 16 �6� × � Reset Ci�c�it Po�t A PA0~PA� EEPROM Stack D�ive� 1�� × � 6-level Inte���pt Po�t B Cont�olle� PB0~PB� USIM D�ive� Watchdog Pin-Sha�ed Time� Po�t C With Po�t A PC0~PC�...

  • Page 9: Pin Description

    BS83B24C/BS83C40C Touch Flash MCU 4� 3� 3� PC1/KEY16 PA5/SDA/SDI/RX/KEY4 PC�/KEY1� � 3� PA4/SDO/TX/KEY3 PC3/KEY1� PA3/SCS/PTP/INT/KEY� PC4/KEY19 PA1/SCK/SCL/PTCK/KEY1 PC5/KEY�0 P�1/KEY40 �9 BS83C40C/BS83CV40C PC6/KEY�1 P�0/KEY39 �� 44 LQFP-A PC�/KEY�� � PE�/KEY3� �� PD0/KEY�3 � PE6/KEY3� �6 PD1/KEY�4 �5 PD�/KEY�5 PA�/SCK/SCL/SDO/TX/XT1/ICPCK/OCDSCK �4 PD3/KEY�6 �3...
  • Page 10 BS83B24C/BS83C40C Touch Flash MCU Pin Name Function Description PAWU Gene�al p��pose I/O. Registe� ena�led p�ll-�p PAPU CMOS and wake-�p. PAS0 PAS0 CMOS SPI se�ial clock I�S PA1/SCK/SCL/ PTCK/KEY1 PAS0 NMOS � C clock line I�S PTCK PAS0 — PTM capt��e inp�t...
  • Page 11 BS83B24C/BS83C40C Touch Flash MCU Pin Name Function Description PAWU Gene�al p��pose I/O. Registe� ena�led p�ll-�p PAPU CMOS and wake-�p. PAS1 PAS1 PA6/INT/KEY5 INTEG — Exte�nal inte���pt INTC0 I�S PAS1 KEY5 — To�ch ke� inp�t 5 TKM1C1 PAWU Gene�al p��pose I/O. Registe� ena�led p�ll-�p PA�...
  • Page 12 BS83B24C/BS83C40C Touch Flash MCU Pin Name Function Description PCPU CMOS Gene�al p��pose I/O. Registe� ena�led p�ll-�p. PCS0 PC1/KEY16 PCS0 KEY16 — To�ch ke� inp�t 16 TKM3C1 PCPU PC� CMOS Gene�al p��pose I/O. Registe� ena�led p�ll-�p. PCS0 PC�/KEY1� PCS0 KEY1� —...
  • Page 13 BS83B24C/BS83C40C Touch Flash MCU BS83C40C Pin Name Function Description PAWU Gene�al p��pose I/O. Registe� ena�led p�ll-�p PAPU CMOS and wake-�p. PAS0 PAS0 NMOS I C data line � I�S PA0/SDA/SDI/RX/ PAS0 — SPI se�ial data inp�t XT�/ICPDA/ I�S OCDSDA PAS0 —...
  • Page 14 BS83B24C/BS83C40C Touch Flash MCU Pin Name Function Description PAWU Gene�al p��pose I/O. Registe� ena�led p�ll-�p PAPU CMOS and wake-�p. PAS1 PAS1 NMOS I � C data line I�S PA5/SDA/SDI/RX/ PAS1 KEY4 — SPI se�ial data inp�t I�S PAS1 — UART se�ial data inp�t I�S...
  • Page 15 BS83B24C/BS83C40C Touch Flash MCU Pin Name Function Description PBPU PB� CMOS Gene�al p��pose I/O. Registe� ena�led p�ll-�p. PBS1 PB�/KEY14 PBS1 KEY14 — To�ch ke� inp�t 14 TKM3C1 PCPU CMOS Gene�al p��pose I/O. Registe� ena�led p�ll-�p. PCS0 PC0/KEY15 PCS0 KEY15 —...
  • Page 16 BS83B24C/BS83C40C Touch Flash MCU Pin Name Function Description PDPU CMOS Gene�al p��pose I/O. Registe� ena�led p�ll-�p. PDS1 PD4/KEY�� PDS1 KEY�� — To�ch ke� inp�t �� TKM6C1 PDPU CMOS Gene�al p��pose I/O. Registe� ena�led p�ll-�p. PDS1 PD5/KEY�� PDS1 KEY�� — To�ch ke� inp�t ��...

  • Page 17: Absolute Maximum Ratings

    BS83B24C/BS83C40C Touch Flash MCU Pin Name Function Description P�PU P�0 CMOS Gene�al p��pose I/O. Registe� ena�led p�ll-�p. P�S0 P�0/KEY39 P�S0 KEY39 — To�ch ke� inp�t 39 TKM9C1 P�PU P�1 CMOS Gene�al p��pose I/O. Registe� ena�led p�ll-�p. P�S0 P�1/KEY40 P�S0 KEY40 —...

  • Page 18: D.c. Characteristics

    BS83B24C/BS83C40C Touch Flash MCU D.C. Characteristics For data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency, pin load conditions, temperature and program instruction type, etc., can all exert an influence on the measured values. Operating Voltage Characteristics Ta=-40°C~�5°C Symbol Parameter Test Conditions Min. Typ. Max. Unit =�MHz �.� — Ope�ating Voltage – HIRC =1�MHz �.� — =16MHz — Ope�ating Voltage – LXT =3��6�Hz �.� —...

  • Page 19: Ope�Ating C

    BS83B24C/BS83C40C Touch Flash MCU Operating Current Characteristics Ta=�5°C Test Conditions Symbol Operating Mode Min. Typ. Max. Unit Conditions �.�V — � SLOW Mode – LIRC =3�kHz — �0 μA — �.�V — � SLOW Mode – LXT =3��6�Hz — �0 μA...

  • Page 20: A.c. Characteristics

    BS83B24C/BS83C40C Touch Flash MCU A.C. Characteristics For data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency and temperature etc., can all exert an influence on the measured values. High Speed Internal Oscillator – HIRC – Frequency Accuracy During the program writing operation the writer will trim the HIRC oscillator at a user selected HIRC frequency and user selected voltage of either 3V or 5V. 8/12/16MHz Test Conditions Symbol Parameter Min. Typ. Max. Unit Temp. �5°C � 3V/5V -40°C ~ �5°C -�% � +�% �MHz w�ite� t�immed HIRC f�eq�enc�...
  • Page 21 BS83B24C/BS83C40C Touch Flash MCU Operating Frequency Characteristic Curves System Operating Frequency 16MHz 1�MHz �MHz 5.5V �.�V �.�V 3.3V Operating Voltage System Start Up Time Characteristics Ta=-40°C~�5°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions — /64� f — —...

  • Page 22: Input/Output Characteristics

    BS83B24C/BS83C40C Touch Flash MCU Input/Output Characteristics Ta=�5°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions — — Inp�t Low Voltage fo� I/O Po�ts — — — 0.�V — — Inp�t High Voltage fo� I/O Po�ts — — 0.�V —...

  • Page 23: Memory Characteristics

    BS83B24C/BS83C40C Touch Flash MCU Memory Characteristics Ta=-40°C~�5°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions fo� Read / W�ite — — — DDmin DDmax Flash Program Memory / Data EEPROM Memory E�ase / W�ite C�cle Time – �lash —...

  • Page 24: System Architecture

    BS83B24C/BS83C40C Touch Flash MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The series of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one or two cycles for most of the standard or extended instructions respectively. The exceptions to this are branch or call instructions which need one more cycle. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator...

  • Page 25: Stack

    BS83B24C/BS83C40C Touch Flash MCU �etch Inst. 1 Exec�te Inst. 1 MOV A�[1�H] �etch Inst. � Exec�te Inst. � � CALL DELAY �etch Inst. 3 �l�sh Pipeline CPL [1�H] �etch Inst. 6 Exec�te Inst. 6 �etch Inst. � 6 DELAY: NOP...

  • Page 26: A�Ithmetic And Logic Unit - Alu

    BS83B24C/BS83C40C Touch Flash MCU P�og�am Co�nte� Top of Stack Stack Level 1 Stack Level � Stack Stack Level 3 P�og�am Pointe� Memo�� Bottom of Stack Stack Level 6 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations:...

  • Page 27: Flash Program Memory

    BS83B24C/BS83C40C Touch Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this series of devices the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, the Flash device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Device Capacity BS�3B�4C 3K × 16 BS�3C40C 4K × 16 Structure The Program Memory has a capacity of 3K×16 or 4K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. BS83B24C BS83C40C 000H 000H Initialisation Vecto� Initialisation Vecto� 004H 004H Inte���pt Vecto�s Inte���pt Vecto�s 01CH 0�0H...
  • Page 28 BS83B24C/BS83C40C Touch Flash MCU The accompanying diagram illustrates the addressing data flow of the look-up table. P�og�am Memo�� Last Page o� TBHP Registe� Data 16 �its TBLP Registe� Use� Selected Registe� TBLH Registe� High B�te Low B�te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is “F00H” refers to the start address of the last page within the 4K Program Memory of the BS83C40C. The table pointer low byte register is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “F06H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address specified by TBLP and TBHP if the “TABRD [m]” or “LTABRD [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRD [m]” or “LTABRD [m]” instruction is executed. Because the TBLH register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the...
  • Page 29 BS83B24C/BS83C40C Touch Flash MCU In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, a means of programming the microcontroller in-circuit has provided using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Flash MCU to Writer Programming Pin correspondence table is as follows: Writer Pins MCU Programming Pins Pin Description ICPDA P�og�amming se�ial data/add�ess ICPCK PA� P�og�amming clock Powe� s�ppl� G�o�nd The Program Memory and EEPROM data Memory can both be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature.

  • Page 30: On-Chip De��G S�Ppo�T Clock Inp�T

    BS83B24C/BS83C40C Touch Flash MCU On-Chip Debug Support – OCDS There are EV chips named BS83BV24C and BS83CV40C which are used to emulate the real MCU devices named BS83B24C and BS83C40C respectively. The EV chip device also provides an “On- Chip Debug” function to debug the device during the development process. The EV chip and the actual MCU device are almost functionally compatible except for the “On-Chip Debug” function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the corresponding document. e-Link Pins EV Chip Pins...

  • Page 31: Data Memory

    Data Memo�� (Secto� 0 ~ Secto� 1) EEC in Secto� 1 ��H �0H Gene�al P��pose Data Memo�� (Secto� 0 ~ Secto� 3) ��H Secto� 0 Secto� 1 Secto� � Secto� 3 Data Memory Structure – BS83B24C Rev. 1.00 �e���a�� 0�� �01�...

  • Page 32: Data Memo

    BS83B24C/BS83C40C Touch Flash MCU To�ch Ke� Data Memo�� (Secto� 5 ~ Secto� 6) Special P��pose Data Memo�� (Secto� 0 ~ Secto� 1) 4�H EEC in Secto� 1 ��H �0H Gene�al P��pose Data Memo�� (Secto� 0 ~ Secto� 5) ��H Secto� 0 Secto�...
  • Page 33 �4H TKM516DH �5H TKM5ROL �6H 3�H PDPU TKM5ROH ��H 3�H SLEDC0 TKM5C0 ��H SLEDC1 TKM5C1 �9H �AH TKM5C� �BH �CH �DH �EH 3�H ��H : Un�sed� �ead as 00H Special Purpose Data Memory – BS83B24C Rev. 1.00 �e���a�� 0�� �01�...
  • Page 34 BS83B24C/BS83C40C Touch Flash MCU Secto� 0 Secto� 1 Secto� 0 Secto� 1 IAR0 PAS0 CTMAH PAS1 TKM616DL 0�H IAR1 PBS0 4�H TKM616DH MP1L PBS1 TKM6ROL MP1H PCS0 PTMC0 TKM6ROH PCS1 PTMC1 TKM6C0 PDS0 PTMDL TKM6C1 0�H TBLP PDS1 4�H PTMDH TKM6C�...

  • Page 35: Special Function Register Description

    BS83B24C/BS83C40C Touch Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional sections however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with the MP1L/MP1H register pair and IAR2 register together with the MP2L/MP2H register pair can access data from any Data Memory Sector. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers will return a result of “00H” and writing to the registers will result in no operation. Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L, MP2H, are provided. These Memory...

  • Page 36: Acc�M�Lato� - Acc

    BS83B24C/BS83C40C Touch Flash MCU Indirect Addressing Program Example 2 data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a, 04h ; setup size of block...

  • Page 37: Stat�S Registe� - Status

    BS83B24C/BS83C40C Touch Flash MCU Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the SC flag, CZ flag, zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/ logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag.
  • Page 38 BS83B24C/BS83C40C Touch Flash MCU In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. • STATUS Register Name PD� “x”: Unknown Bit 7 SC: The result of the “XOR” operation which is performed by the OV flag and the MSB of the instruction operation result. CZ: The operational result of different flags for different instructions. Bit 6 For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/SBCM/LSBC/LSBCM instructions, the CZ flag is the “AND” operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag will not be affected. Bit 5 TO: Watchdog Time-Out Flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power Down Flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3 OV: Overflow Flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2...

  • Page 39: Eeprom Data Memory

    BS83B24C/BS83C40C Touch Flash MCU EEPROM Data Memory Each device contains an area of internal EEPROM Data Memory. EEPROM is by its nature a non- volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 128×8 bits. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and a data register in Sector 0 and a single control register in Sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Sector 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Sector 1, can be read...

  • Page 40: Reading Data F�Om The Eeprom

    BS83B24C/BS83C40C Touch Flash MCU • EEC Register Name — — — — WREN RDEN — — — — — — — — Bit 7~4 Unimplemented, read as “0” Bit 3 WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data...

  • Page 41: W�Iting Data To The Eeprom

    BS83B24C/BS83C40C Touch Flash MCU Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be reset...
  • Page 42 BS83B24C/BS83C40C Touch Flash MCU Programming Examples Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, 40H ; setup memory pointer MP1L MOV MP1L, A ; MP1L points to EEC register MOV A, 01H ; setup memory pointer MP1H MOV MP1H, A SET IAR1.1 ; set RDEN bit, enable read operations SET IAR1.0 ; start Read Cycle - set RD bit BACK: SZ IAR1.0 ; check for read cycle end...

  • Page 43: Oscillators

    BS83B24C/BS83C40C Touch Flash MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through relevant control registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillator requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are...

  • Page 44: Inte�Nal Rc Oscillato� - Hirc

    BS83B24C/BS83C40C Touch Flash MCU /� High Speed Oscillato� /� HIRCEN HIRC IDLE0 P�escale� SLEEP /3� Low Speed �SS Oscillato�s LXTEN CKS�~CKS0 IDLE� SLEEP LIRC LIRC System Clock Configurations Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of 8/12/16 MHz, which is selected using a configuration option. The HIRC1~HIRC0 bits in the HIRCC register must also be setup to match the selected configuration option frequency. Setting up these bits is necessary to ensure that the HIRC frequency accuracy specified in the A.C. Characteristics is achieved. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 3V or 5V and at a temperature...

  • Page 45: Inte�Nal 3�Khz Oscillato� - Lirc

    BS83B24C/BS83C40C Touch Flash MCU The pin-shared software control bits determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins or other pin-shared functional pins. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O pins or other pin-shared functional pins. • If the LXT oscillator is used for any clock source, the 32.768 kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resisters along with interconnecting lines are all located as close to the MCU as possible. Internal Oscillator Circuit 3�.�6� Inte�nal RC Oscillato� To inte�nal ci�c�its XT� C� Note: 1. R � R � C1 and C� a�e �eq�i�ed. �. Altho�gh not shown XT1/XT� pins have a pa�asitic capacitance of a�o�nd �p�.

  • Page 46: Operating Modes And System Clocks

    BS83B24C/BS83C40C Touch Flash MCU Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. As both high and low speed clock sources are provided the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The devices have different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock selections using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, f , or low frequency, f , source, and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is sourced from the HIRC oscillator. The low speed system clock source can be sourced from the internal clock f . If f is selected then it can be sourced from the LXT or LIRC oscillator, selected by the FSS bit in the SCC register. The other choice, which is a divided version of the high...

  • Page 47: S�Stem Ope�Ation Modes

    BS83B24C/BS83C40C Touch Flash MCU System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the FAST Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0,...
  • Page 48 BS83B24C/BS83C40C Touch Flash MCU IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU will be switched off but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. IDLE2 Mode The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. Control Registers The registers, SCC, HIRCC and LXTC, are used to control the system clock and the corresponding oscillator configurations. Register Name CKS� CKS1 CKS0 — — �SS �HIDEN �SIDEN HIRCC — — — — HIRC1 HIRC0 HIRC� HIRCEN LXTC —...
  • Page 49 BS83B24C/BS83C40C Touch Flash MCU FSIDEN: Low Frequency oscillator control when CPU is switched off Bit 0 0: Disable 1: Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an “HALT” instruction. • HIRCC Register Name — — — — HIRC1 HIRC0 HIRC� HIRCEN — — — — — — — — Bit 7~4 Unimplemented, read as “0” Bit 3~2 HIRC1~HIRC0: HIRC Frequency selection 00: 8MHz 01: 12MHz 10: 16MHz 11: 8MHz When the HIRC oscillator is enabled or the HIRC frequency selection is changed by application program, the clock frequency will automatically be changed after the HIRCF flag is set to 1.

  • Page 50: Ope�Ating Mode Switching

    BS83B24C/BS83C40C Touch Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the FAST Mode and SLOW Mode is executed using the CKS2~CKS0 bits in the SCC register while Mode Switching from the FAST/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register. FAST SLOW CPU ��n CPU ��n on/off SLEEP IDLE0 HALT inst��ction exec�ted HALT inst��ction exec�ted CPU stop CPU stop �HIDEN=0 �HIDEN=0 �SIDEN=0 �SIDEN=1 IDLE2 IDLE1 HALT inst��ction exec�ted...
  • Page 51 BS83B24C/BS83C40C Touch Flash MCU FAST Mode to SLOW Mode Switching When running in the FAST Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the CKS2~CKS0 bits to “111” in the SCC register. This will then use the low speed system oscillator...
  • Page 52 BS83B24C/BS83C40C Touch Flash MCU SLOW Mode to FAST Mode Switching In SLOW mode the system clock is derived from f . When system clock is switched back to the FAST mode from f , the CKS2~CKS0 bits should be set to “000” ~ “110” and then the system clock will respectively be switched to f ~ f /64. However, if f is not used in SLOW mode and thus switched off, it will take some time to re- oscillate and stabilise when switching to the FAST mode from the SLOW Mode. This is monitored using the HIRCF bit in the HIRCC register. The time duration required for the high speed system oscillator stabilization is specified in the relevant characteristics. SLOW Mode CKS�~CKS0 = 000~110 FAST Mode �HIDEN=0� �SIDEN=0 HALT inst��ction is exec�ted SLEEP Mode �HIDEN=0� �SIDEN=1 HALT inst��ction is exec�ted...
  • Page 53 BS83B24C/BS83C40C Touch Flash MCU Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the FHIDEN bit in the SCC register equal to “0” and the FSIDEN bit in the SCC register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The f clock will be stopped and the application program will stop at the “HALT” instruction, but the f clock will be on. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting as the WDT function is always enabled. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The f and f clocks will be on but the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition.

  • Page 54: Stand

    BS83B24C/BS83C40C Touch Flash MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LXT or LIRC oscillator has been enabled. In the IDLE1 and IDLE2 Mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow When the device executes the “HALT” instruction, the PDF flag will be set to 1. The PDF flag will be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up that only resets the Program Counter and Stack Pointer, other flags remain in their original status.

  • Page 55: Watchdog Timer

    BS83B24C/BS83C40C Touch Flash MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal RC oscillator, f . The LIRC internal LIRC oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with V , temperature and process variations. The Watchdog Timer source clock is then subdivided by a ratio of 2 to 2 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable and reset MCU operation. • WDTC Register Name WE� WS� Bit 7~3 WE4~WE0: WDT function software control 10101/01010: Enable Others: Reset MCU When these bits are changed by the environmental noise or software setting to reset the microcontroller, the reset operation will be activated after a delay time, t...

  • Page 56: Watchdog Time� Ope�Ation

    BS83B24C/BS83C40C Touch Flash MCU WRF: WDT Control Register Software Reset Flag Bit 0 0: Not occur 1: Occurred This bit is set high by the WDT Control register software reset and cleared to 0 by the application program. Note that this bit can only be cleared to zero by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTC register to offer the enable and reset control of the Watchdog Timer. The WDT function will be enabled if the WE4~WE0 bits are equal to 10101B or 01010B. If the WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the device after a delay time, t . After power on these bits will have a value of 01010B. SRESET WE4 ~ WE0 Bits WDT Function 10101B o� 01010B Ena�le An� othe� val�es Reset MCU...

  • Page 57: Reset And Initialisation

    BS83B24C/BS83C40C Touch Flash MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. The Watchdog Timer overflow is one of many reset types and will reset the microcontroller. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. All types of reset operations result in different register conditions being setup. Reset Functions There are several ways in which a microcontroller reset can occur through events occurring internally.
  • Page 58 BS83B24C/BS83C40C Touch Flash MCU • RSTC Register Name RSTC� RSTC6 RSTC5 RSTC4 RSTC3 RSTC� RSTC1 RSTC0 Bit 7~0 RSTC7~RSTC0: Reset Function Control 01010101: No operation 10101010: No operation Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after a delay time, t and the SRESET RSTF bit in the RSTFC register will be set to 1. • RSTFC Register Name — — — — RST� LVR� LR� WR� — —...
  • Page 59 BS83B24C/BS83C40C Touch Flash MCU • LVRC Register Name LVS� LVS6 LVS5 LVS4 LVS3 LVS� LVS1 LVS0 LVS7~LVS0: LVR voltage select Bit 7~0 01010101B: 2.1V 00110011B: 2.55V 10011001B: 3.15V 10101010B: 3.8V Other values: MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after the low voltage condition keeps more than a t time. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined LVR values above, will also result in the generation of an MCU reset. The reset operation will be activated after a delay time,...

  • Page 60: Reset Initial Conditions

    BS83B24C/BS83C40C Touch Flash MCU Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset in the FAST mode or SLOW mode is the same as LVR reset except that the Watchdog time-out flag TO will be set high. WDT Time-o�t RSTD Inte�nal Reset WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to zero and the TO flag will be set high. Refer to the System Start Up Time Characteristics for t details. WDT Time-o�t Inte�nal Reset...
  • Page 61 BS83B24C/BS83C40C Touch Flash MCU LVR Reset WDT Time-out Register Reset WDT Time-out (Normal (Normal Name (Power On) (IDLE/SLEEP) Operation) Operation) IAR0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 �...
  • Page 62 BS83B24C/BS83C40C Touch Flash MCU LVR Reset WDT Time-out Register Reset WDT Time-out (Normal (Normal Name (Power On) (IDLE/SLEEP) Operation) Operation) ● - - - - - - 1 1 - - - - - - 1 1 - - - - - - 1 1 - - - - - - �...
  • Page 63 BS83B24C/BS83C40C Touch Flash MCU LVR Reset WDT Time-out Register Reset WDT Time-out (Normal (Normal Name (Power On) (IDLE/SLEEP) Operation) Operation) ● - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - �...
  • Page 64 BS83B24C/BS83C40C Touch Flash MCU LVR Reset WDT Time-out Register Reset WDT Time-out (Normal (Normal Name (Power On) (IDLE/SLEEP) Operation) Operation) TKM4C� ● ● 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 �...

  • Page 65: Input/Output Ports

    — — — — PDC1 PDC0 PDPU — — — — — — PDPU1 PDPU0 “—”: Unimplemented I/O Logic Function Register List – BS83B24C Register Name PA� PA� PAC� PAC5 PAC5 PAC4 PAC3 PAC� PAC1 PAC0 PAPU PAPU� PAPU4 PAPU5...

  • Page 66: P�Ll-High Resisto�S

    BS83B24C/BS83C40C Touch Flash MCU Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using the relevant pull-high control registers and are implemented using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as a digital input or NMOS output. Otherwise, the pull-high resistors cannot be enabled. • PxPU Register Name PxPU� PxPU6 PxPU5 PxPU4 PxPU3 PxPU� PxPU1 PxPU0 PxPUn: I/O Port x Pin Pull-high Function Control 0: Disable 1: Enable The PxPUn bit is used to control the pin pull-high function.Here the “x” can be A, B, C, D, E or F respectively depending upon the selected device. However, the actual available bits for each I/O port may be different. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register.
  • Page 67 BS83B24C/BS83C40C Touch Flash MCU I/O Port Control Registers Each I/O port has its own control register which controls the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. • PxC Register Name PxC� PxC5 PxC5 PxC4 PxC3 PxC� PxC1...
  • Page 68 BS83B24C/BS83C40C Touch Flash MCU SLEDC01~SLEDC00: PA3~PA0 Source Current Selection Bit 1~0 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.) • SLEDC1 Register – BS83B24C Name — — SLEDC15 SLEDC14 SLEDC13 SLEDC1� SLEDC11 SLEDC10 — — — — Bit 7~6 Unimplemented, read as “0” SLEDC15~SLEDC14: PD1~PD0 Source Current Selection Bit 5~4 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.) SLEDC13~SLEDC12: PC7~PC4 Source Current Selection Bit 3~2 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.)

  • Page 69: Pin-Sha�Ed

    BS83B24C/BS83C40C Touch Flash MCU • SLEDC2 Register – BS83C40C Name — — SLEDC�5 SLEDC�4 SLEDC�3 SLEDC�� SLEDC�1 SLEDC�0 — — — — Bit 7~6 Unimplemented, read as “0” Bit 5~4 SLEDC25~SLEDC24: PF1~PF0 Source Current Selection 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.) Bit 3~2 SLEDC23~SLEDC22: PE7~PE4 Source Current Selection 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.) Bit 1~0 SLEDC21~SLEDC20: PE3~PE0 Source Current Selection 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.)
  • Page 70 — — — — PDS03 PDS0� PDS01 PDS00 I�S — — — — — I�S� I�S1 I�S0 Pin-shared Function Selection Register List – BS83B24C Register Name PAS0 PAS0� PAS06 PAS05 PAS04 PAS03 PAS0� PAS01 PAS00 PAS1 PAS1� PAS16 PAS15 PAS14 PAS13 PAS1�...
  • Page 71 BS83B24C/BS83C40C Touch Flash MCU • PAS1 Register Name PAS1� PAS16 PAS15 PAS14 PAS13 PAS1� PAS11 PAS10 Bit 7~6 PAS17~PAS16: PA7 pin-shared function selection 00/01/10: PA7/ PTPI 11: KEY6 Bit 5~4 PAS15~PAS14: PA6 pin-shared function selection 00/01/10: PA6/INT 11: KEY5 Bit 3~2 PAS13~PAS12: PA5 pin-shared function selection 00/10: PA5 01: SDA/SDI/RX 11: KEY4 PAS11~PAS10: PA4 pin-shared function selection Bit 1~0 00/10: PA4 01: SDO/TX 11: KEY3 • PBS0 Register Name PBS0� PBS06...
  • Page 72 PCS11 PCS10 Bit 7~6 PCS17~PCS16: PC7 pin-shared function selection 00/01/10: PC7 11: KEY22 Bit 5~4 PCS15~PCS14: PC6 pin-shared function selection 00/01/10: PC6 11: KEY21 Bit 3~2 PCS13~PCS12: PC5 pin-shared function selection 00/01/10: PC5 11: KEY20 Bit 1~0 PCS11~PCS10: PC4 pin-shared function selection 00/01/10: PC4 11: KEY19 • PDS0 Register – BS83B24C Name — — — — PDS03 PDS0� PDS01 PDS00 — — — — — — — —...
  • Page 73 BS83B24C/BS83C40C Touch Flash MCU • PDS0 Register – BS83C40C Name PDS0� PDS06 PDS05 PDS04 PDS03 PDS0� PDS01 PDS00 Bit 7~6 PDS07~PDS06: PD3 pin-shared function selection 00/01/10: PD3 11: KEY26 Bit 5~4 PDS05~PDS04: PD2 pin-shared function selection 00/01/10: PD2 11: KEY25 Bit 3~2 PDS03~PDS02: PD1 pin-shared function selection 00/01/10: PD1 11: KEY24 Bit 1~0 PDS01~PDS00: PD0 pin-shared function selection 00/01/10: PD0 11: KEY23 • PDS1 Register – BS83C40C Name PDS1�...
  • Page 74 BS83B24C/BS83C40C Touch Flash MCU PES01~PES00: PE0 pin-shared function selection Bit 1~0 00/01/10: PE0 11: KEY31 • PES1 Register – BS83C40C Name PES1� PES16 PES15 PES14 PES13 PES1� PES11 PES10 PES17~PES16: PE7 pin-shared function selection Bit 7~6 00/01/10: PE7 11: KEY38 PES15~PES14: PE6 pin-shared function selection Bit 5~4 00/01/10: PE6 11: KEY37 PES13~PES12: PE5 pin-shared function selection Bit 3~2 00/01/10: PE5 11:KEY36 PES11~PES10: PE4 pin-shared function selection Bit 1~0 00/01: PE4 10: CTPB 11: KEY35 • PFS0 Register – BS83C40C Name —...
  • Page 75 BS83B24C/BS83C40C Touch Flash MCU I/O Pin Structures The accompanying diagram illustrates the internal structures of the I/O logic function. As the exact logical construction of the I/O pin will differ from this diagram, it is supplied as a guide only to assist with the functional understanding of the logic function I/O pins. The wide range of pin-shared structures does not permit all types to be shown. P�ll-high Registe� Weak Cont�ol Bit Select P�ll-�p Data B�s W�ite Cont�ol Registe� Chip Reset I/O pin Read Cont�ol Registe� Data Bit W�ite Data Registe� Read Data Registe� S�stem Wake-�p PA onl�...

  • Page 76: Timer Modules - Tm

    BS83B24C/BS83C40C Touch Flash MCU Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. To implement time related functions the devices include several Timer Modules, generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact and Periodic Type TM sections. Introduction These devices contain several TMs and each individual TM can be categorised as a certain type, namely Compact Type TM or Periodic Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact and Periodic type TMs will be described in this section and the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the two types of TMs are summarised in the accompanying table. TM Function Time�/Co�nte� √ √ Inp�t Capt��e — √ Compa�e Match O�tp�t √ √ PWM Channels Single P�lse O�tp�t...

  • Page 77: Tm Inte

    BS83B24C/BS83C40C Touch Flash MCU TM Interrupts The Compact or Periodic type TM has two internal interrupt, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has an TM input pin, with the label xTCK. The xTM input pin, xTCK, is essentially a clock source for the xTM and is selected using the xTCK2~xTCK0 bits in the xTMC0 register. This external TM input pin allows an external clock source to drive the internal TM. The xTCK input pin can be chosen to have either a rising or falling active edge. The PTCK pin is also used as the external trigger input pin in single pulse output mode for the PTM. The Periodic type TM has another input pin, PTPI, which is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the PTIO1~PTIO0 bits in the PTMC1 register. The TMs each has two output pins, xTP and xTPB. The TM output pin can be selected using the corresponding pin-shared function selection bits described in the Pin-shared Function section. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external xTP and xTPB output pins are also the pins where the TM generates the PWM output waveform. As the TM input/output pins are pin-shared with other functions, the TM input/output function must first be setup using relevant pin-shared function selection register. The details of the pin-shared function selection are described in the pin-shared function section. Device Input Output Input Output BS�3B�4C — — PTCK� PTPI PTP� PTPB BS�3C40C...
  • Page 78 BS83B24C/BS83C40C Touch Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the “MOV” instruction to access the CCRA and CCRP low byte registers, named xTMAL and PTMRPL, using the following access procedures. Accessing the CCRA and CCRP low byte registers without following these access procedures will result in unpredictable values. xTM Co�nte� Registe� (Read onl�) xTMDL xTMDH �-�it B�ffe� xTMAL xTMAH xTM CCRA Registe� (Read/W�ite) PTMRPL PTMRPH PTM CCRP Registe� (Read/W�ite) Data B�s The following steps show the read and write procedures: • Writing Data to CCRA or CCRP...

  • Page 79: Compact Type Tm - Ctm

    BS83B24C/BS83C40C Touch Flash MCU Compact Type TM – CTM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact Type TM can also be controlled with an external input pin and can drive two external output pins. CCRP Compa�ato� P Match CTMP� Inte���pt 3-�it Compa�ato� P CTOC ��~�9 O�tp�t Pola�it� Co�nte� Clea�...
  • Page 80 BS83B24C/BS83C40C Touch Flash MCU • CTMC0 Register Name CTPAU CTCK� CTCK1 CTCK0 CTON CTRP� CTRP1 CTRP0 Bit 7 CTPAU: CTM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the CTM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. CTCK2~CTCK0: Select CTM Counter clock Bit 6~4 000: f 001: f 010: f 011: f 100: f 101: f 110: CTCK rising edge clock 111: CTCK falling edge clock These three bits are used to select the clock source for the CTM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source is the system clock, while f and f are other internal clocks, the details of which can be found in the oscillator section.
  • Page 81 BS83B24C/BS83C40C Touch Flash MCU • CTMC1 Register Name CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR Bit 7~6 CTM1~CTM0: Select CTM Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the CTM. To ensure reliable operation the CTM should be switched off before any changes are made to the CTM1 and CTM0 bits. In the Timer/Counter Mode, the CTM output pin state is undefined. Bit 5~4 CTIO1~CTIO0: Select CTP output function Compare Match Output Mode...
  • Page 82 BS83B24C/BS83C40C Touch Flash MCU CTOC: CTP Output control bit Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode 0: Active low 1: Active high This is the output control bit for the CTM output pin. Its operation depends upon whether CTM is being used in the Compare Match Output Mode or in the PWM Output Mode. It has no effect if the CTM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the CTM output pin before a compare match occurs. In the PWM Output Mode it determines if the PWM...

  • Page 83: Compact T�Pe Tm Ope�Ating Modes

    BS83B24C/BS83C40C Touch Flash MCU • CTMAL Register Name D� D� Bit 7~0 CTM CCRA Low Byte Register bit 7 ~ bit 0 CTM 10-bit CCRA bit 7 ~ bit 0 • CTMAH Register Name — — — — — — D� — — — — — — — — — — — — Bit 7~2 Unimplemented, read as “0” Bit 1~0 CTM CCRA High Byte Register bit 1 ~ bit 0...
  • Page 84 BS83B24C/BS83C40C Touch Flash MCU Co�nte� ove�flow Co�nte� Val�e CTCCLR = 0; CTM [1:0] = 00 CCRP > 0 CCRP=0 Co�nte� clea�ed �� CCRP val�e 0x3�� CCRP > 0 Co�nte� Res�me Resta�t CCRP Pa�se Stop CCRA Time CTON CTPAU CTPOL CCRP Int. flag CTMP�...
  • Page 85 BS83B24C/BS83C40C Touch Flash MCU Co�nte� Val�e CTCCLR = 1; CTM [1:0] = 00 CCRA = 0 CCRA > 0 Co�nte� clea�ed �� CCRA val�e Co�nte� ove�flow 0x3�� CCRA=0 Res�me CCRA Pa�se Stop Co�nte� Resta�t CCRP Time CTON CTPAU CTPOL No CTMA� flag gene�ated on...
  • Page 86 BS83B24C/BS83C40C Touch Flash MCU Timer/Counter Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the CTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the CTM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 10 respectively. The PWM function within the CTM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the CTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output Mode, the CTCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register. The PWM...
  • Page 87 BS83B24C/BS83C40C Touch Flash MCU Co�nte� Val�e CTDPX = 0; CTM [1:0] = 10 Co�nte� clea�ed �� CCRP Co�nte� Reset when CTON �et��ns high CCRP Co�nte� Stop if Pa�se Res�me CTON �it low CCRA Time CTON CTPAU CTPOL CCRA Int. flag CTMA�...
  • Page 88 BS83B24C/BS83C40C Touch Flash MCU Co�nte� Val�e CTDPX = 1; CTM [1:0] = 10 Co�nte� clea�ed �� CCRA Co�nte� Reset when CTON �et��ns high CCRA Co�nte� Stop if Pa�se Res�me CTON �it low CCRP Time CTON CTPAU CTPOL CCRP Int. flag CTMP�...

  • Page 89: Periodic Type Tm - Ptm

    BS83B24C/BS83C40C Touch Flash MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic Type TM can also be controlled with two external input pins and can drive two external output pin. CCRP Compa�ato� P Match 10-�it Compa�ato� P PTMP� Inte���pt PTOC �0~�9 O�tp�t Pola�it� Co�nte� Clea� 10-�it Co�nt-�p Co�nte� Cont�ol Cont�ol Cont�ol PTPB PTON PTCCLR PTPAU PTM1~PTM0 PTPOL PxSn �0~�9...

  • Page 90: Pe�Iodic T�Pe Tm Registe� Desc�Iption

    BS83B24C/BS83C40C Touch Flash MCU Periodic Type TM Register Description Overall operation of the Periodic Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name PTMC0 PTPAU PTCK� PTCK1 PTCK0 PTON — — — PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR PTMDL D� D� PTMDH — — —...
  • Page 91 BS83B24C/BS83C40C Touch Flash MCU • PTMRPL Register Name D� D� Bit 7~0 PTM CCRP Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRP bit 7 ~ bit 0 • PTMRPH Register Name — — — — — — D� — — — — — — — — — — — — Bit 7~2 Unimplemented, read as “0” Bit 1~0 PTM CCRP High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRP bit 9 ~ bit 8 •...
  • Page 92 BS83B24C/BS83C40C Touch Flash MCU • PTMC1 Register Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR Bit 7~6 PTM1~PTM0: Select PTM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTM. To ensure reliable operation the PTM should be switched off before any changes are made to the PTM1 and PTM0 bits. In the Timer/Counter Mode, the PTM output pin state is undefined. Bit 5~4 PTIO1~PTIO0: Select PTM external pin PTP or PTPI function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of PTPI or PTCK 01: Input capture at falling edge of PTPI or PTCK...
  • Page 93 BS83B24C/BS83C40C Touch Flash MCU PTOC: PTM PTP Output control Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTM output pin. Its operation depends upon whether PTM is being used in the Compare Match Output Mode or in the PWM Output Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/...

  • Page 94: Pe�Iodic T�Pe Tm Ope�Ation Modes

    BS83B24C/BS83C40C Touch Flash MCU Periodic Type TM Operation Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register. Compare Match Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMAF and PTMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTCCLR is high no PTMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to “0”. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the PTM output pin will change state. The PTM output pin condition however only changes state when a PTMAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM output pin. The way in which the PTM output pin changes state are determined by the condition of the PTIO1 and PTIO0 bits in the PTMC1 register. The PTM output pin can be selected using the PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTM output pin, which is setup after the PTON bit changes from low to high, is setup using the PTOC bit. Note that if the PTIO1 and PTIO0 bits are zero then no pin change will take place.
  • Page 95 BS83B24C/BS83C40C Touch Flash MCU Co�nte� ove�flow Co�nte� Val�e PTCCLR = 0; PTM [1:0] = 00 CCRP > 0 CCRP=0 Co�nte� clea�ed �� CCRP val�e 0x3�� CCRP > 0 Co�nte� Res�me Resta�t CCRP Pa�se Stop CCRA Time PTON PTPAU PTPOL CCRP Int.
  • Page 96 BS83B24C/BS83C40C Touch Flash MCU Co�nte� Val�e PTCCLR = 1; PTM [1:0] = 00 CCRA = 0 CCRA > 0 Co�nte� clea�ed �� CCRA val�e Co�nte� ove�flow 0x3�� CCRA=0 Res�me CCRA Pa�se Stop Co�nte� Resta�t CCRP Time PTON PTPAU PTPOL No PTMA� flag gene�ated on...
  • Page 97 BS83B24C/BS83C40C Touch Flash MCU Timer/Counter Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the PTM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 10 respectively. The PWM function within the PTM is useful for applications which require functions such as motor control, heating control, illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the PTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output mode, the PTCCLR bit has no effect as the PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can...
  • Page 98 BS83B24C/BS83C40C Touch Flash MCU Co�nte� Val�e PTM [1:0] = 10 Co�nte� clea�ed �� CCRP Co�nte� Reset when PTON �et��ns high CCRP Co�nte� Stop if Pa�se Res�me PTON �it low CCRA Time PTON PTPAU PTPOL CCRA Int. �lag PTMA� CCRP Int.
  • Page 99 BS83B24C/BS83C40C Touch Flash MCU Single Pulse Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin. The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which can be implemented using the application program. However in the Single Pulse Output Mode, the PTON bit can also be made to automatically change from low to high using the external PTCK pin, which will in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTM interrupt. The counter can only be reset back to zero when the PTON bit changes from low to high when the counter restarts. In the Single Pulse Output Mode CCRP is not used. The PTCCLR is not used in this Mode. CCRA CCRA Leading Edge T�ailing Edge S/W Command S/W Command SET“PTON” CLR“PTON” PTON �it PTON �it o�...
  • Page 100 BS83B24C/BS83C40C Touch Flash MCU Co�nte� Val�e PTM [1:0] = 10 ; PTIO [1:0] = 11 Co�nte� stopped �� CCRA Co�nte� Reset when PTON �et��ns high CCRA Co�nte� Stops �� Res�me Pa�se softwa�e CCRP Time PTON A�to. set �� PTCK pin Softwa�e...
  • Page 101 BS83B24C/BS83C40C Touch Flash MCU Capture Input Mode To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPI or PTCK pin, selected by the PTCAPTS bit in the PTMC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register. The counter is started when the PTON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPI or PTCK pin the present value in the counter will be latched into the CCRA registers and a PTM interrupt generated. Irrespective of what events occur on the PTPI or PTCK pin the counter will continue to free run until the PTON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI or PTCK pin to be a rising edge, falling edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPI or PTCK pin, however it must be noted that the counter will continue to run. As the PTPI or PTCK pin is pin shared with other functions, care must be taken if the PTM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTCCLR, PTOC and PTPOL bits are not used in this Mode. Rev. 1.00 �e���a�� 0�� �01�...
  • Page 102 BS83B24C/BS83C40C Touch Flash MCU Co�nte� Val�e PTM [1:0] = 01 Co�nte� clea�ed �� CCRP Co�nte� Co�nte� Stop Reset CCRP Res�me Pa�se Time PTON PTPAU Active Active Active edge edge edge PTM capt��e pin PTPI o� PTCK CCRA Int. �lag PTMA�...

  • Page 103: Universal Serial Interface Module - Usim

    BS83B24C/BS83C40C Touch Flash MCU Universal Serial Interface Module – USIM The devices contain a Universal Serial Interface Module, which includes the four-line SPI interface, the two-line I C interface and the two-line UART interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI, I C or UART based hardware such as sensors, Flash or EEPROM memory, etc. The USIM interface pins are pin-shared with other I/O pins therefore the USIM interface functional pins must first be selected using the corresponding pin-shared function selection bits. As all the interface types share the same...
  • Page 104 BS83B24C/BS83C40C Touch Flash MCU SPI Maste� SPI Slave SPI Master/Slave Connection Data B�s SIMD SDI Pin TX/RX Shift Registe� SDO Pin Clock CKEG Edge/Pola�it� CKPOLB Cont�ol B�s� WCOL Stat�s TR� SIMIC� SCK Pin Clock So��ce Select PTM CCRP match f�eq�enc�/�...
  • Page 105 BS83B24C/BS83C40C Touch Flash MCU • SIMD Register Name D� D� “x”: Unknown D7~D0: USIM SPI/I Bit 7~0 C data register bit 7 ~ bit 0 SPI Control Registers There are also two control registers for the SPI interface, SIMC0 and SIMC2. The SIMC0 register is used to control the enable/disable function and to set the data transmission clock frequency. The SIMC2 register is used for other control functions such as LSB/MSB selection, write collision flag etc. • SIMC0 Register Name SIM� SIM1 SIM0 SIMDEB1 SIMDEB0 SIMEN SIMIC� Bit 7~5 SIM2~SIM0: USIM SPI/I C Operating Mode Control 000: SPI master mode; SPI clock is f 001: SPI master mode; SPI clock is f 010: SPI master mode; SPI clock is f 011: SPI master mode; SPI clock is f 100: SPI master mode; SPI clock is PTM CCRP match frequency/2...
  • Page 106 BS83B24C/BS83C40C Touch Flash MCU SIMEN: USIM SPI/I Bit 1 C Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the USIM SPI/I C interface. When the SIMEN bit is cleared to zero to disable the USIM SPI/I C interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I C function and the USIM operating current will be reduced to a minimum value. When the bit is high the USIM SPI/I interface is enabled. If the USIM is configured to operate as an SPI interface via the UMD and SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the USIM is configured to operate as an I C interface via the UMD and SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 SIMICF: USIM SPI Incomplete Flag 0: USIM SPI incomplete condition is not occurred 1: USIM SPI incomplete condition is occurred This bit is only available when the USIM is configured to operate in an SPI slave mode. If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program. • SIMC2 Register Name D�...
  • Page 107 BS83B24C/BS83C40C Touch Flash MCU MLS: SPI data shift order Bit 3 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. CSEN: SPI SCS pin control Bit 2 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and used as a select pin. Bit 1 WCOL: SPI write collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared to 0 by the application program. Bit 0 TRF: SPI Transmit/Receive complete flag 0: SPI data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set “1” automatically when an SPI data transmission is completed, but must set to “0” by the application program. It can be used to generate an interrupt. SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is completed, the TRF flag will be set high automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate...
  • Page 108 BS83B24C/BS83C40C Touch Flash MCU SIMEN=1� CSEN=0 (Exte�nal P�ll-high) SIMEN� CSEN=1 SCK (CKPOLB=1� CKEG=0) SCK (CKPOLB=0� CKEG=0) SCK (CKPOLB=1� CKEG=1) SCK (CKPOLB=0� CKEG=1) SDO (CKEG=0) D�/D0 D6/D1 D5/D� D4/D3 D3/D4 D�/D5 D1/D6 D0/D� SDO (CKEG=1) D�/D0 D6/D1 D5/D� D4/D3 D3/D4 D�/D5 D1/D6 D0/D�...
  • Page 109 BS83B24C/BS83C40C Touch Flash MCU SPI T�ansfe� W�ite Data UMD=0 Clea� WCOL into SIMD Maste� Slave Maste� o� Slave WCOL=1? SIM[�:0]=000� 001� SIM[�:0]=101 010� 011 o� 100 T�ansmission completed? (TR�=1?) Config��e CKPOLB� Read Data CKEG� CSEN and MLS f�om SIMD SIMEN=1 Clea�...
  • Page 110 BS83B24C/BS83C40C Touch Flash MCU SPI Operation Steps All communication is carried out using the 4-line interface for either Master or Slave Mode. The CSEN bit in the SIMC2 register controls the overall function of the SPI interface. Setting this bit high will enable the SPI interface by allowing the SCS line to be active, which can then be used to control the SPI interface. If the CSEN bit is low, the SPI interface will be disabled and the SCS line will be in a floating condition and can therefore not be used for control of the SPI interface. If the CSEN bit and the SIMEN bit in the SIMC0 are set high, this will place the SDI line in a floating condition and the SDO line high. If in Master Mode the SCK line will be either high or low depending upon the clock polarity selection bit CKPOLB in the SIMC2 register. If in Slave Mode the SCK line will be in a floating condition. If the SIMEN bit is low, then the bus will be disabled and SCS, SDI, SDO and SCK will all become I/O pins or the other functions using the corresponding pin-shared control bits. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SIMD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode. Master Mode • Step 1 Select the SPI Master mode and clock source using the UMD and SIM2~SIM0 bits in the SIMC0 control register. • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Slave devices. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then use the SCK and SCS lines to output the data. After this, go to step 5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register.

  • Page 111: I � C Inte�Face

    BS83B24C/BS83C40C Touch Flash MCU Slave Mode • Step 1 Select the SPI Slave mode using the UMD and SIM2~SIM0 bits in the SIMC0 control register • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Master devices. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCK and SCS signal. After this, go to step 5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a USIM SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. Error Detection The WCOL bit in the SIMC2 register is provided to indicate errors during data transfer. The bit is...
  • Page 112 BS83B24C/BS83C40C Touch Flash MCU C Interface Operation The I C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I C bus is identified by a unique address which will be transmitted and received on the I C bus. When two devices communicate with each other on the bidirectional I C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For the device, which only operates in slave mode, there are two methods of transferring data on the I C bus, the slave transmit mode and the slave receive mode. The pull-high control function pin-shared with SCL/SDA pin is still applicable even if I C device is activated and the related internal pull-high register could be controlled by its corresponding pull-high control register. Data B�s � � C Data Registe� C Add�ess Registe� (SIMD) (SIMA) Add�ess HAAS Add�ess Match–...
  • Page 113 BS83B24C/BS83C40C Touch Flash MCU The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I C interface. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 2 or 4 system clocks. To achieve the required I C data transfer speed, there exists a relationship between the system clock, f , and the I C debounce time. For either the I Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. C Debounce Time Selection C Standard Mode (100kHz) C Fast Mode (400kHz) No De�o�nce > � MHz > 5 MHz � s�stem clock de�o�nce > 4 MHz >...
  • Page 114 BS83B24C/BS83C40C Touch Flash MCU • SIMA Register Name SIMA6 SIMA5 SIMA4 SIMA3 SIMA� SIMA1 SIMA0 Bit 7~1 SIMA6~SIMA0: I C slave address SIMA6~SIMA0 is the I C slave address bit 6~bit 0. Bit 0 D0: Reserved bit, can be read or written C Control Registers There are three control registers for the I C interface, SIMC0, SIMC1 and SIMTOC. The SIMC0 register is used to control the enable/disable function and to set the data transmission clock frequency. The SIMC1 register contains the relevant flags which are used to indicate the I...
  • Page 115 BS83B24C/BS83C40C Touch Flash MCU SIMEN: USIM SPI/I Bit 1 C Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the USIM SPI/I C interface. When the SIMEN bit is cleared to zero to disable the USIM SPI/I C interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I C function and the USIM operating current will be reduced to a minimum value. When the bit is high the USIM SPI/I interface is enabled. If the USIM is configured to operate as an SPI interface via the UMD and SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the USIM is configured to operate as an I C interface via the UMD and SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 SIMICF: USIM SPI Incomplete Flag This bit is only available when the USIM is configured to operate in an SPI slave mode. Refer to the SPI register section. • SIMC1 Register Name HC� HAAS TXAK IAMWU...
  • Page 116 BS83B24C/BS83C40C Touch Flash MCU SRW: I Bit 2 C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data...
  • Page 117 BS83B24C/BS83C40C Touch Flash MCU Sta�t CLR UMD SET SIM[�:0]=110 SET SIMEN W�ite Slave Add�ess to SIMA � C B�s Inte���pt=? CLR USIME SET USIME Poll USIM� to decide Wait fo� Inte���pt � when to go to I C B�s ISR Go to Main P�og�am...
  • Page 118 BS83B24C/BS83C40C Touch Flash MCU C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave...
  • Page 119 BS83B24C/BS83C40C Touch Flash MCU Sta�t SIMTO�=1? SET SIMTOEN HAAS=1? CLR SIMTO� HTX=1? SRW=1? RETI Read f�om SIMD to CLR HTX �elease SCL Line SET HTX CLR TXAK RETI W�ite data to SIMD to D�mm� �ead f�om SIMD �elease SCL Line to �elease SCL Line...
  • Page 120 BS83B24C/BS83C40C Touch Flash MCU Sta�t Slave Add�ess � C time-o�t co�nte� sta�t Stop � C time-o�t co�nte� �eset on SCL negative t�ansition C Time-out When an I C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the USIM interrupt vector. When an I C time-out occurs, the I C internal circuitry will be reset and the registers will be reset into the following condition: Registers After I C Time-out SIMD� SIMA� SIMC0...
  • Page 121 BS83B24C/BS83C40C Touch Flash MCU UART Interface The devices contain an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function shares the same internal interrupt vector with the SPI and I C interfaces which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, asynchronous communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits • Baud rate generator with 8-bit prescaler...
  • Page 122 BS83B24C/BS83C40C Touch Flash MCU UART External Pins To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. The TX and RX pin function should first be selected by the corresponding pin-shared function selection register before the UART function is used. Along with the UMD bit, the UREN bit, the UTXEN and URXEN bits, if set, will setup these pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX and RX pins. When the TX or RX pin function is disabled by clearing the UMD, UREN, UTXEN or URXEN bit, the TX or RX pin will be set to a floating state. At this time whether the internal pull-high resistor is connected to the TX or RX pin or not is determined by the corresponding I/O pull-high function control bit. UART Data Transfer Scheme The above block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the UTXR_RXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the UTXR_RXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal UTXR_ RXR register, where it is buffered and can be manipulated by the application program. Only the UTXR_RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception only exists as a single shared register in the Data Memory. This shared register known as the UTXR_RXR register is used for both data transmission and data reception. UART Status and Control Registers There are six control registers associated with the UART function. The UMD bit in the SIMC0...
  • Page 123 BS83B24C/BS83C40C Touch Flash MCU • SIMC0 Register Name SIM� SIM1 SIM0 SIMDEB1 SIMDEB0 SIMEN SIMIC� Bit 7~5 SIM2~SIM0: USIM SPI/I C Operating Mode Control When the UMD bit is cleared to zero, these bits setup the SPI or I C operating mode of the USIM function. Refer to the SPI or I C register section for more details. Bit 4 UMD: UART mode selection bit 0: SPI or I C mode 1: UART mode This bit is used to select the UART mode. When this bit is cleared to zero, the actual SPI or I C mode can be selected using the SIM2~SIM0 bits. Note that the UMD bit must be set low for SPI or I C mode. Bit 3~2 SIMDEB1~SIMDEB0: I C Debounce Time Selection Refer to the I C register section. Bit 1 SIMEN: USIM SPI/I C Enable Control This bit is only available when the USIM is configured to operate in an SPI or I mode with the UMD bit set low. Refer to the SPI or I...
  • Page 124 BS83B24C/BS83C40C Touch Flash MCU UFERR: Framing error flag Bit 5 0: No framing error is detected 1: Framing error is detected The UFERR flag is the framing error flag. When this read only flag is “0”, it indicates that there is no framing error. When the flag is “1”, it indicates that a framing error has been detected for the current character. The flag can also be cleared to 0 by a software sequence which will involve a read to the status register UUSR followed by an access to the UTXR_RXR data register. UOERR: Overrun error flag Bit 4 0: No overrun error is detected 1: Overrun error is detected The UOERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is “0”, it indicates that there is no overrun error. When the flag is “1”, it indicates that an overrun error occurs which will inhibit further transfers to the UTXR_RXR receive data register. The flag is cleared to 0 by a software sequence, which is a read to the status register UUSR followed by an access to the UTXR_RXR data register. Bit 3 URIDLE: Receiver status 0: Data reception is in progress (Data being received) 1: No data reception is in progress (Receiver is idle) The URIDLE flag is the receiver status flag. When this read only flag is “0”, it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is “1”, it indicates that the receiver is idle.
  • Page 125 BS83B24C/BS83C40C Touch Flash MCU • UUCR1 Register The UUCR1 register together with the UUCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below: Name UREN UBNO UPREN UPRT USTOPS UTXBRK URX� UTX� “x”: Unknown UREN: UART function enable control Bit 7 0: Disable UART. TX and RX pins are in a floating state 1: Enable UART. TX and RX pins function as UART pins The UREN bit is the UART enable bit. When this bit is equal to “0”, the UART will be disabled and the RX pin as well as the TX pin will be set in a floating state. When the bit is equal to “1”, the UART will be enabled if the UMD bit is set and the TX and RX pins will function as defined by the UTXEN and URXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the UTXEN, URXEN, UTXBRK, URXIF, UOERR, UFERR, UPERR and UNF bits will be cleared to 0, while the UTIDLE, UTXIF and URIDLE bits will be set. Other control bits in UUCR1, UUCR2 and UBRG registers will remain unaffected. If the UART is active and the UREN bit is cleared to 0, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re- enabled, it will restart in the same configuration.
  • Page 126 BS83B24C/BS83C40C Touch Flash MCU URX8: Receive data bit 8 for 9-bit data transfer format (read only) Bit 1 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as URX8. The UBNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Bit 0 UTX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as UTX8. The UBNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. • UUCR2 Register The UUCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various USIM UART mode interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below: Name UTXEN URXEN UBRGH UADDEN UWAKE URIE UTIIE UTEIE Bit 7 UTXEN: UART Transmitter enabled control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named UTXEN is the Transmitter Enable Bit. When this bit is equal to “0”, the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be set in a floating state. If the UTXEN bit is equal to “1” and the UMD and UREN bit are also equal to “1”, the transmitter will be enabled and the TX pin will be controlled by the UART.
  • Page 127 BS83B24C/BS83C40C Touch Flash MCU UADDEN: Address detect function enable control Bit 4 0: Address detect function is disabled 1: Address detect function is enabled The bit named UADDEN is the address detect function enable control bit. When this bit is equal to “1”, the address detect function is enabled. When it occurs, if the 8th bit, which corresponds to URX7 if UBNO=0 or the 9th bit, which corresponds to URX8 if UBNO=1, has a value of “1”, then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of UBNO. If the address bit known as the 8th or 9th bit of the received word is “0” with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. Bit 3 UWAKE: RX pin wake-up UART function enable control 0: RX pin wake-up UART function is disabled 1: RX pin wake-up UART function is enabled This bit is used to control the wake-up UART function when a falling edge on the RX pin occurs. Note that this bit is only available when the UART clock (f ) is switched off. There will be no RX pin wake-up UART function if the UART clock (f ) exists. If the UWAKE bit is set to 1 as the UART clock (f ) is switched off, a UART wake- up request will be initiated when a falling edge on the RX pin occurs. When this request happens and the corresponding interrupt is enabled, an RX pin wake-up...
  • Page 128 BS83B24C/BS83C40C Touch Flash MCU • UTXR_RXR Register The UTXR_RXR register is the data register which is used to store the data to be transmitted on the TX pin or being received from the RX pin. Name UTXRX� UTXRX6 UTXRX5 UTXRX4 UTXRX3 UTXRX� UTXRX1 UTXRX0 “x”: Unknown Bit 7~0 UTXRX7~UTXRX0: UART Transmit/Receive Data bit 7 ~ bit 0 • UBRG Register Name UBRG� UBRG6 UBRG5 UBRG4 UBRG3 UBRG� UBRG1 UBRG0 “x”: Unknown Bit 7~0 UBRG7~UBRG0: Baud Rate values By programming the UBRGH bit in UUCR2 Register which allows selection of the related formula described above and programming the required value in the UBRG register, the required baud rate can be setup.
  • Page 129 BS83B24C/BS83C40C Touch Flash MCU UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding UBNO, UPRT, UPREN, and USTOPS bits in the UUCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UART transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/Disabling the UART Interface The basic on/off function of the internal UART function is controlled using the UREN bit in the UUCR1 register. When the UART mode is selected by setting the UMD bit in the SIMC0 register to “1”, if the UREN, UTXEN and URXEN bits are set, then these two UART pins will act as normal...
  • Page 130 BS83B24C/BS83C40C Touch Flash MCU The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. Next Pa�it� Bit Sta�t Sta�t Stop Bit 0 Bit 1 Bit � Bit 3 Bit 4 Bit 5 Bit 6 Bit � 8-bit Data Format Next Pa�it� Bit Sta�t Sta�t Stop Bit 0 Bit 1 Bit �...
  • Page 131 BS83B24C/BS83C40C Touch Flash MCU The read-only UTXIF flag is set by the UART hardware and if set indicates that the UTXR_RXR register is empty and that other data can now be written into the UTXR_RXR register without overwriting the previous data. If the UTEIE bit is set then the UTXIF flag will generate an interrupt. During a data transmission, a write instruction to the UTXR_RXR register will place the data into the UTXR_RXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the UTXR_RXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the UTXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the UTIDLE bit will be set. To clear the UTIDLE bit the following software sequence is used: 1. A UUSR register access 2. A UTXR_RXR register write execution Note that both the UTXIF and UTIDLE bits are cleared by the same software sequence.
  • Page 132 BS83B24C/BS83C40C Touch Flash MCU • Make the correct selection of UBNO, UPRT and UPREN bits to define the word length, parity type. • Setup the UBRG register to select the desired baud rate. • Set the URXEN bit to ensure that the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received the following sequence of events will occur: • The URXIF bit in the UUSR register will be set when the UTXR_RXR register has data available. There will be at most one more character available before an overrun error occurs. • When the contents of the shift register have been transferred to the UTXR_RXR register, then if the URIE bit is set, an interrupt will be generated. • If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set. The URXIF bit can be cleared using the following software sequence: 1. A UUSR register access 2. A UTXR_RXR register read execution Receive Break Any break character received by the UART will be managed as a framing error. The receiver...
  • Page 133 BS83B24C/BS83C40C Touch Flash MCU Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – UOERR The UTXR_RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the UTXR_RXR register. If this is not done, the overrun error flag UOERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The UOERR flag in the UUSR register will be set. • The UTXR_RXR contents will not be lost. • The shift register will be overwritten. • An interrupt will be generated if the URIE bit is set. The UOERR flag can be cleared by an access to the UUSR register followed by a read to the UTXR_RXR register.
  • Page 134 BS83B24C/BS83C40C Touch Flash MCU UART Interrupt Structure Several individual UART conditions can trigger an USIM interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if the global interrupt enable bit and the USIM interrupt control bit are enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding UUSR register flags which will generate an USIM interrupt if its associated interrupt enable control bit in the UUCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual USIM UART mode interrupt sources. The address detect condition, which is also an USIM UART mode interrupt source, does not have an associated flag, but will generate an USIM interrupt when an address detect condition occurs if its function is enabled by setting the UADDEN bit in the UUCR2 register. An RX pin wake-up, which is also an USIM UART mode interrupt source, does not have an associated flag, but will generate an USIM interrupt if the UART clock (f ) source is switched off and the UWAKE and URIE bits in the UUCR2 register are set when a falling edge on the RX pin occurs. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for the oscillator to restart and stabilize before the system resumes normal operation. Note that the UUSR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared...
  • Page 135 BS83B24C/BS83C40C Touch Flash MCU Address Detect Mode Setting the Address Detect Mode bit, UADDEN, in the UUCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the URXIF flag. If the UADDEN bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the USIME and EMI interrupt enable bits must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if UBNO=1 or the 8th bit if UBNO=0. If this bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the UADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the URXIF flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit UPREN to zero. Bit 9 if UBNO=1, USIM Interrupt UADDEN Bit 8 if UBNO=0 Generated √ √ × √ UADDEN Bit Function UART Power Down and Wake-up...

  • Page 136: Uart Inte�Face

    BS83B24C/BS83C40C Touch Flash MCU Touch Key Function Each device provides multiple touch key functions. The touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. Touch Key Structure The touch keys are pin-shared with the I/O pins, with the desired function chosen via the corresponding selection register bits. Keys are organised into several groups, with each group known as a module and having a module number, M0 to Mn. Each module is a fully independent set of four Touch Keys and each Touch Key has its own oscillator. Each module contains its own control logic circuits and register set. Examination of the register names will reveal the module number it is referring to. Total Key Device Touch Key Module...
  • Page 137 BS83B24C/BS83C40C Touch Flash MCU Ke� KEY 1 TKMn16DH / TKMn16DL ( to Data Memo�� Secto� 5) Ke� KEY � M�x . M�lti- C�TMCK �ilte� 16-�it C/� Co�nte� TKC�OV f�eq�enc� Ke� KEY 3 Mn�ILEN MnD�EN Ke� KEY 4 TKMnC� TKMnROH / TKMnROL Mn�ILEN...

  • Page 138: Touch Key Register Definition

    BS83B24C/BS83C40C Touch Flash MCU Touch Key Register Definition Each touch key module, which contains four touch key functions, has its own suite registers. The following table shows the register set for each touch key module. The Mn within the register name refers to the Touch Key module number. The series of devices has up to ten Touch Key Modules depending upon the selected device. Name Description TKTMR To�ch ke� time slot �-�it co�nte� p�eload �egiste� TKC0 To�ch ke� f�nction Cont�ol �egiste� 0 TKC1 To�ch ke� f�nction Cont�ol �egiste� 1 TK16DL To�ch ke� f�nction 16-�it co�nte� low ��te TK16DH To�ch ke�...
  • Page 139 BS83B24C/BS83C40C Touch Flash MCU • TKC0 Register Name TKRAMC TKRCOV TKST TKC�OV TK16OV — TKMOD TKBUSY — — Bit 7 TKRAMC: Touch key data memory access control 0: Accessed by MCU 1: Accessed by touch key module This bit determines that the touch key data memory is used by the MCU or the touch key module. However, the touch key module will have the priority to access the touch key data memory when the touch key module operates in the auto scan mode, i.e., the TKST bit state is changed from 0 to 1 when the TKMOD bit is set low. After the touch key auto scan operation is completed, i.e., the TKBUSY bit state is changed from 1 to 0, the touch key data memory access will be controlled by the TKRAMC bit. Therefore, it is recommended to set the TKRAMC bit to 1 when the touch key module operates in the auto scan mode. Otherwise, the contents of the touch key data memory may be modified as this data memory space is configured by the touch key module followed by the MCU access. Bit 6 TKRCOV: Touch key time slot counter overflow flag 0: No overflow occurs 1: Overflow occurs This bit can be accessed by application program. Note that this bit can not be set by application program but must be cleared to 0 by application program. In the auto scan mode, if module 0 or all module time slot counter, selected by the TSCS bit, overflows but touch key scan is not completed, the TKRCOV bit will not...
  • Page 140 BS83B24C/BS83C40C Touch Flash MCU TK16OV: Touch key function 16-bit counter overflow flag Bit 3 0: No overflow occurs 1: Overflow occurs This bit is set high by the touch key function 16-bit counter overflow and must be cleared to 0 by application programs. Bit 2 Unimplemented, read as “0” TKMOD: Touch key scan mode selection Bit 1 0: Auto scan mode 1: Manual scan mode In the manual scan mode the reference oscillator capacitor value should be properly configured before the scan operation begins and the touch key module 16-bit C/F counter value should be read after the scan operation finishes by application program. In the auto scan mode the data movement which is described above is implemented by hardware. The individual reference oscillator capacitor value and 16-bit C/F counter content for all scanned keys will be read from and written into a dedicated Touch Key Data Memory area. The scan operation will not be stopped until all arranged keys are scanned. Bit 0 TKBUSY: Touch key scan operation busy flag 0: Not busy – no scan operation is executed or scan operation is completed 1: Busy – scan operation is executing This bit indicates whether the touch key scan operation is executing or not. It is set to 1 when the TKST bit is set high to start the scan operation for all touch key scan modes. In the auto scan mode this bit is cleared to 0 automatically when the touch key scan operation is completed. In the manual scan mode this bit is cleared to 0 automatically when the touch key time slot counter overflows. • TKC1 Register Name D� TSCS TK16S1 TK16S0 TK�S1...
  • Page 141 BS83B24C/BS83C40C Touch Flash MCU • TK16DH/TK16DL – Touch Key Function 16-bit Counter Register Pair Register TK16DH TK16DL Name D15 D14 D13 D1� D11 D10 D9 D� D� D� This register pair is used to store the touch key function 16-bit counter value. This 16-bit counter can be used to calibrate the reference or key oscillator frequency. When the touch key time slot counter overflows in the manual scan mode, this 16-bit counter will be stopped and the counter content will be unchanged. However, this 16-bit counter content will be cleared to zero at the end of the time slot 0, slot 1 and slot 2 but kept unchanged at the end of the time slot 3 in the auto scan mode. This register pair will be cleared to zero when the TKST bit is set low. • TKMn16DH/TKMn16DL – Touch Key Module n 16-bit C/F Counter Register Pair...
  • Page 142 BS83B24C/BS83C40C Touch Flash MCU MnFILEN: Touch key module n filter function control Bit 4 0: Disable 1: Enable MnSOFC: Touch key module n C-to-F oscillator frequency hopping function control select Bit 3 0: Controlled by the MnSOF2~MnSOF0 1: Controlled by hardware circuit This bit is used to select the touch key oscillator frequency hopping function control method. When this bit is set to 1, the key oscillator frequency hopping function is controlled by the hardware circuit regardless of the MnSOF2~MnSOF0 bits value. Bit 2~0 MnSOF2~MnSOF0: Touch key module n Reference and Key oscillators hopping frequency select 000: 1.020MHz 001: 1.040MHz 010: 1.059MHz 011: 1.074MHz 100: 1.085MHz 101: 1.099MHz 110: 1.111MHz 111: 1.125MHz The frequency which is mentioned here will be changed when the external or internal capacitor is with different value. If the touch key operates at 1MHz frequency, users can adjust the frequency in scale when select other frequency. • TKMnC1 Register Name MnTSS — MnROEN MnKOEN MnK4EN MnK3EN MnK�EN MnK1EN —...
  • Page 143 BS83B24C/BS83C40C Touch Flash MCU MnK4EN: Touch key module n KEY4 enable control Bit 3 Touch Key Module n – Mn MnK4EN 0: Disa�le I/O o� othe� f�nctions 1: Ena�le KEY4 KEY� KEY1� KEY16 KEY�0 KEY�4 KEY�� KEY3� KEY36 KEY40 BS�3B�4C √ √ √ √ √ √ — —...

  • Page 144: To�Ch Ke� Ope�Ation

    BS83B24C/BS83C40C Touch Flash MCU MnSK11~MnSK10: Touch key module n time slot 1 key scan selection Bit 3~2 00: KEY1 01: KEY2 10: KEY3 11: KEY4 These bits are used to select the desired scan key in time slot 1 and only available in the auto scan mode. MnSK01~MnSK00: Touch key module n time slot 0 key scan selection Bit 1~0 00: KEY1 01: KEY2 10: KEY3 11: KEY4 These bits are used to select the desired scan key in time slot 0 in the auto scan mode or used as the multiplexer for scan key selection in the manual mode. Touch Key Operation When a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase. By using this capacitance variation to change slightly the frequency of the internal sense oscillator, touch actions can be sensed by measuring these frequency changes. Using an internal programmable divider the reference clock is used to generate a fixed time period. By counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined. Each touch key module contains four touch key inputs which are shared with logical I/O pins, and the desired function is selected using register bits. Each touch key has its own independent sense oscillator. Therefore, there are four sense oscillators within each touch key module. TKST MnKOEN MnROEN Ha�dwa�e set to “0” KEY OSC CLK Refe�ence OSC CLK...
  • Page 145 BS83B24C/BS83C40C Touch Flash MCU During this reference clock fixed interval, the number of clock cycles generated by the sense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. At the end of the fixed reference clock time interval a Touch Key interrupt signal will be generated. Using the TSCS bit in the TKC1 register can select the module 0 time slot counter as the time slot counter for all modules. All modules use the same started signal, TKST, in the TKC0 register. The touch key module 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unit period counter in all modules will be automatically cleared when the TKST bit is cleared to zero, but the 8-bit programmable time slot counter will not be cleared. The overflow time is setup by user. When the TKST bit changes from low to high, the 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically switched on. The key oscillator and reference oscillator in all modules will be automatically stopped and the 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically switched off when the time slot counter overflows. The clock source for the time slot counter is sourced from the reference oscillator or f /4 which is selected using the MnTSS bit in the TKMnC1 register. The reference oscillator and key oscillator will be enabled by setting the MnROEN bit and MnKOEN bits in the TKMnC1 register. When the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. Each touch key module consists of four touch keys, KEY1~KEY4 are contained in module 0, KEY5~KEY8 are contained in module 1, KEY9~KEY12 are contained in module 2, etc. Each touch...
  • Page 146 BS83B24C/BS83C40C Touch Flash MCU Ke� A�to Scan C�cle TKST Time slot 0 Time slot 1 Time slot 1 Mod�le 0 Time slot � Time slot � Time slot 3 Time slot 3 Time slot 0 Time slot 1 Time slot 1 Mod�le 1...
  • Page 147 BS83B24C/BS83C40C Touch Flash MCU Touch Key Data Memory The devices provide two dedicated Data Memory areas for the touch key auto scan mode. One area is used to store the 16-bit C/F counter values of the touch key module and located in Data Memory Sector 5. The other area is used to store the reference oscillator internal capacitor values of the touch key module and located in Data Memory Sector 6. 16-bit C/F counter value Ref. OSC Capacitor value (Sector 5) (Sector 6) TKM016DL_K1 TKM0ROL_K1 TKM016DH_K1 TKM0ROH_K1 0�H TKM016DL_K� TKM0ROL_K� TKM016DH_K� TKM0ROH_K� Module 0 TKM016DL_K3 TKM0ROL_K3 TKM016DH_K3 TKM0ROH_K3 TKM016DL_K4...
  • Page 148 BS83B24C/BS83C40C Touch Flash MCU Touch Key Scan Operation Flowchart Sta�t W�ite Ref. OSC Capacito� to TKMnROH/TKMnROL To�ch Ke� Man�al Scan Ope�ation Sta�t Set Sta�t �it TKST 0 B�s� flag TKBUSY=1 Initiate Time Slot & 16-�it C/� Co�nte� All Time Slot &...
  • Page 149 BS83B24C/BS83C40C Touch Flash MCU Sta�t W�ite Ref. OSC inte�nal Capacito� val�e to Data Memo�� (Secto� 6 ) To�ch Ke� A�to Scan Ope�ation Sta�t Set Sta�t �it TKST 0 B�s� flag TKBUSY=1 Load Ref. OSC inte�nal Capacito� val�e f�om Data Memo�� (Secto� 6 ) Sto�e C/�...

  • Page 150: To�Ch Ke� Inte

    BS83B24C/BS83C40C Touch Flash MCU Touch Key Interrupt The touch key only has single interrupt, when the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. The 16-bit C/F counter, 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot counter in all modules will be automatically cleared. The TKCFOV flag which is the 16-bit C/F counter overflow flag will go high when any of the Touch Key Module 16-bit C/F counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. The TK16OV flag which is the 16-bit counter overflow flag will go high when the 16-bit counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. More details regarding the touch key interrupt is located in the interrupt section of the datasheet. Programming Considerations After the relevant registers are setup, the touch key detection process is initiated the changing the TKST Bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV flag which is the time slot counter flag will go high when the counter overflows. When this happens an interrupt signal will be generated. When the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency.

  • Page 151: Interrupts

    — — — INTS1 INTS0 INTC0 — M�0� TKM� INT� M�0E TKME INTE INTC1 DE� TB1� TB0� USIM� TB1E TB0E USIME M�I0 — — PTMA� PTMP� — — PTMAE PTMPE Interrupt Register List – BS83B24C Rev. 1.00 �e���a�� 0�� �01�...
  • Page 152 BS83B24C/BS83C40C Touch Flash MCU Register Name INTEG — — — — — — INTS1 INTS0 INTC0 — M�0� TKM� INT� M�0E TKME INTE INTC1 DE� TB1� TB0� USIM� TB1E TB0E USIME INTC� — — — M�1� — — — M�1E M�I0...
  • Page 153 BS83B24C/BS83C40C Touch Flash MCU • INTC1 Register Name DE� TB1� TB0� USIM� TB1E TB0E USIME Bit 7 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 6 TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 5 TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 4 USIMF: USIM Module interrupt request flag 0: No request 1: Interrupt request DEE: Data EEPROM interrupt control Bit 3 0: Disable 1: Enable TB1E: Time Base 1 interrupt control Bit 2 0: Disable 1: Enable TB0E: Time Base 0 interrupt control...

  • Page 154: Inte

    BS83B24C/BS83C40C Touch Flash MCU PTMPF: PTM Comparator P match interrupt request flag Bit 4 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1 PTMAE: PTM Comparator A match interrupt control 0: Disable 1: Enable Bit 0 PTMPE: PTM Comparator P match interrupt control 0: Disable 1: Enable • MFI1 Register – BS83C40C Name — — CTMA� CTMP� — — CTMAE CTMPE — — — — — — — —...
  • Page 155 Inte���pts contained within M�lti-��nction Inte���pts Time Base 0 TB0� TB0E 1�H Time Base 1 TB1� TB1E EEPROM DE� Interrupt Structure – BS83B24C EMI a�to disa�led in ISR Legend xx� Req�est �lag� no a�to �eset in ISR Inte���pt Req�est Ena�le Maste� Vecto� P�io�it�...

  • Page 156: Exte�Nal Inte

    BS83B24C/BS83C40C Touch Flash MCU External Interrupt The external interrupts are controlled by signal transitions on the INT pin. An external interrupt request will take place when the external interrupt request flag, INTF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INTE, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function.

  • Page 157: Eeprom Inte

    BS83B24C/BS83C40C Touch Flash MCU Timer Module Interrupts The Compact and Periodic type TMs each has two interrupts, one comes from the comparator A match situation and the other comes from the comparator P match situation. All of the TM interrupts are contained within the Multi-function Interrupts. For all of the TM types there are two interrupt request flags and two enable control bits. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. EEPROM Interrupt An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector will take place. When the EEPROM Interrupt is serviced, the DEF flag will be automatically cleared, the EMI bit will also be automatically cleared to disable other interrupts. USIM Interrupt The Universal Serial Interface Module Interrupt, also known as the USIM interrupt, will take place when the USIM Interrupt request flag, USIMF, is set. As the USIM interface can operate in three modes which are SPI mode, I C mode and UART mode, the USIMF flag can be set by different conditions depending on the selected interface mode. If the SPI or I C mode is selected, the USIM interrupt can be triggered when a byte of data has been received or transmitted by the USIM SPI or I C interface, or an I...
  • Page 158 BS83B24C/BS83C40C Touch Flash MCU Touch Key Interrupt An Touch Key Interrupt request will take place when the Touch Key Interrupt request flag, TKMF, is set, which occurs when the touch key time slot counter overflows. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Touch Key Interrupt enable bit, TKME, must first be set. When the interrupt is enabled, the stack is not full and the touch key time slot counter overflows, a subroutine call to the Touch Key Interrupt vector, will take place. When the Touch Key Interrupt is serviced, the TKRMF flag will be automatically cleared, the EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TBnF, will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI, and Time Base enable bits, TBnE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TBnF, will be automatically cleared, the EMI bit will also be automatically cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, f , originates from the internal clock source f /4 or f and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBnC registers to obtain longer interrupt periods whose value ranges. The clock cource which in turn controls the Time Base interrupt period is selected using the CLKSEL[1:0] bits in the PSCR register.

  • Page 159: Inte

    BS83B24C/BS83C40C Touch Flash MCU • TB0C Register Name TB0ON — — — — TB0� TB01 TB00 — — — — — — — — Bit 7 TB0ON: Time Base 0 Control 0: Disable 1: Enable Bit 6~3 Unimplemented, read as “0” Bit 2~0 TB02~TB00: Select Time Base 0 Time-out Period 000: 2 001: 2 010: 2 011: 2 100: 2 101: 2 110: 2 111: 2 •...

  • Page 160: P�Og�Amming Conside�Ations

    BS83B24C/BS83C40C Touch Flash MCU Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program.

  • Page 161: Application Circuits

    BS83B24C/BS83C40C Touch Flash MCU Application Circuits KEY1 KEY� 0.1µ� KEY3 KEY4 PA0/SDA/SDI/RX/ XT�/ICPDA/OCDSDA KEY�1 PA�/SCK/SCL/SDO/TX/ XT1/ICPCK/OCDSCK KEY�� KEY�3 KEY�4 BS83B24C KEY1 KEY� 0.1µ� KEY3 KEY4 PA0/SDA/SDI/RX/ XT�/ICPDA/OCDSDA KEY3� PA�/SCK/SCL/SDO/TX/ XT1/ICPCK/OCDSCK KEY3� KEY39 KEY40 BS83C40C Rev. 1.00 �e���a�� 0�� �01�...

  • Page 162: Instruction Set

    BS83B24C/BS83C40C Touch Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to...

  • Page 163: Logical And Rotate Ope�Ation

    BS83B24C/BS83C40C Touch Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one Bit right or left. Different...

  • Page 164: Instruction Set Summary

    BS83B24C/BS83C40C Touch Flash MCU Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic Z� C� AC� OV� SC Add Data Memo�� to ACC ADD A�[m] Note Z� C� AC� OV� SC ADDM A�[m]...
  • Page 165 BS83B24C/BS83C40C Touch Flash MCU Mnemonic Description Cycles Flag Affected Data Move MOV A�[m] Move Data Memo�� to ACC None MOV [m]�A Move ACC to Data Memo�� Note None MOV A�x Move immediate data to ACC None Bit Operation CLR [m].i Clea�...

  • Page 166: Extended Inst

    BS83B24C/BS83C40C Touch Flash MCU Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Arithmetic � Z� C� AC� OV� SC LADD A�[m] Add Data Memo��...
  • Page 167 BS83B24C/BS83C40C Touch Flash MCU Mnemonic Description Cycles Flag Affected Branch LSZ [m] Skip if Data Memo�� is ze�o � Note None LSZA [m] Skip if Data Memo�� is ze�o with data movement to ACC � Note None LSNZ [m] Skip if Data Memo�� is not ze�o �...

  • Page 168: Instruction Definition

    BS83B24C/BS83C40C Touch Flash MCU Instruction Definition Add Data Memory to ACC with Carry ADC A,[m] Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C, SC ADD A,x Add immediate data to ACC Description The contents of the Accumulator and the specified immediate data are added.
  • Page 169 BS83B24C/BS83C40C Touch Flash MCU CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared.
  • Page 170 BS83B24C/BS83C40C Touch Flash MCU DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ← [m] − 1 Affected flag(s) DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ← [m] − 1 Affected flag(s) Enter power down mode HALT Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO ← 0 PDF ← 1 Affected flag(s) TO, PDF INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. Operation [m] ← [m] + 1 Affected flag(s)
  • Page 171 BS83B24C/BS83C40C Touch Flash MCU NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ [m] Affected flag(s) Logical OR immediate data to ACC OR A,x Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ x Affected flag(s) ORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. Operation [m] ← ACC ″OR″ [m] Affected flag(s) Return from subroutine...
  • Page 172 BS83B24C/BS83C40C Touch Flash MCU RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 Affected flag(s) None Rotate Data Memory left through Carry RLC [m] Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 Affected flag(s) RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 Affected flag(s) RR [m]...
  • Page 173 BS83B24C/BS83C40C Touch Flash MCU RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 Affected flag(s) SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] − C Affected flag(s) OV, Z, AC, C, SC, CZ Subtract immediate data from ACC with Carry SBC A, x Description The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC - [m] - C Affected flag(s)
  • Page 174 BS83B24C/BS83C40C Touch Flash MCU Set Data Memory SET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ← 1 Affected flag(s) None SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] + 1 Skip if [m]=0 Affected flag(s) None SIZA [m] Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified...
  • Page 175 BS83B24C/BS83C40C Touch Flash MCU SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − x Affected flag(s) OV, Z, AC, C, SC, CZ SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 ↔ [m].7~[m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
  • Page 176 BS83B24C/BS83C40C Touch Flash MCU TABRD [m] Read table (specific page) to TBLH and Data Memory Description The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None ITABRD [m] Increment table pointer low byte first and read table to TBLH and Data Memory Description Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None Increment table pointer low byte first and read table (last page) to TBLH and Data Memory ITABRDL [m]...

  • Page 177: Extended Instruction Definition

    BS83B24C/BS83C40C Touch Flash MCU Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC LADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC LADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C, SC LADDM A,[m]...
  • Page 178 BS83B24C/BS83C40C Touch Flash MCU LCPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] ← [m] Affected flag(s) LCPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) LDAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H...
  • Page 179 BS83B24C/BS83C40C Touch Flash MCU LMOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None LMOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] ← ACC Affected flag(s) None LOR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ [m] Affected flag(s) LORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. Operation [m] ← ACC ″OR″ [m] Affected flag(s)
  • Page 180 BS83B24C/BS83C40C Touch Flash MCU LRR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 Affected flag(s) None LRRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None LRRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 Affected flag(s) LRRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces...
  • Page 181 BS83B24C/BS83C40C Touch Flash MCU LSDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] − 1 Skip if [m]=0 Affected flag(s) None LSDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None Set Data Memory LSET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None Set bit of Data Memory LSET [m].i...
  • Page 182 BS83B24C/BS83C40C Touch Flash MCU LSNZ [m] Skip if Data Memory is not 0 Description If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m] ≠ 0 Affected flag(s) None LSUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ LSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ LSWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
  • Page 183 BS83B24C/BS83C40C Touch Flash MCU LSZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i=0 Affected flag(s) None LTABRD [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LTABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LITABRD [m] Increment table pointer low byte first and read table to TBLH and Data Memory...

  • Page 184: Package Information

    BS83B24C/BS83C40C Touch Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 1�4 �e���a�� 0�� �01�...

  • Page 185: Pin Sop (300Mil) O�Tline Dimensions

    BS83B24C/BS83C40C Touch Flash MCU 28-pin SOP (300mil) Outline Dimensions &  " Dimensions in inch Symbol Min. Nom. Max. — 0.406 BSC — — 0.�95 BSC — 0.01� — 0.0�0 C’ — 0.�05 BSC — — — 0.104 — 0.050 BSC —...
  • Page 186 BS83B24C/BS83C40C Touch Flash MCU 28-pin SSOP (150mil) Outline Dimensions &  " Dimensions in inch Symbol Min. Nom. Max. — 0.�36 BSC — — 0.154 BSC — 0.00� — 0.01� C’ — 0.390 BSC — — — 0.069 — 0.0�5 BSC —...
  • Page 187 BS83B24C/BS83C40C Touch Flash MCU 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.4�� BSC — — 0.394 BSC — — 0.4�� BSC — — 0.394 BSC — — 0.03� BSC — � 0.01� 0.015 0.01�...
  • Page 188 Howeve�� Holtek ass�mes no �esponsi�ilit� a�ising f�om the �se of the specifications described. The applications mentioned herein are used solely fo� the p��pose of ill�st�ation and Holtek makes no wa��ant� o� �ep�esentation that s�ch applications will �e s�ita�le witho�t f��the� modification� no� �ecommends the �se of its p�od�cts fo�...

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