Holtek BS86DH12C Manual page 91

BS86DH12C
High Voltage Touch A/D Flash MCU with HVIO
Register
Name
7
PTMC0 PTPAU
PTMC1 PTM1
PTMDL D7
PTMDH —
PTMAL D7
PTMAH —
PTMRPL PTRP7
PTMRPH —
• PTMC0 Register
Bit 7
Name PTPAU
R/W R/W
POR 0
PTPAU: PTM counter pause control
Bit 7
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the PTM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes to
a low value again.
Bit 6~4 PTCK2~PTCK0: PTM Counter clock selection
000: f
001: f
010: f
011: f
100: f
101: f
110: PTCK rising edge clock
111: PTCK falling edge clock
These three bits are used to select the clock source for the PTM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source f
the system clock, while f
be found in the oscillator section.
Bit 3 PTON: PTM counter on/off control
0: Off
1: On
This bit controls the overall on/off function of the PTM. Setting the bit high enables
the counter to run while clearing the bit disables the PTM. Clearing this bit to zero
will stop the counter from counting and turn off the PTM which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again. If the PTM is in
the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode
then the PTM output pin will be reset to its initial condition, as specified by the PTOC
bit, when the PTON bit changes from low to high.
Bit 2~0 Unimplemented, read as "0"
Rev. 1.00
6 5 4
PTCK2 PTCK1 PTCK0
PTM0 PTIO1 PTIO0
D6 D5 D4
— — —
D6 D5 D4
— — —
PTRP6 PTRP5 PTRP4
— — —
10-bit Periodic TM Register List
6 5 4
PTCK2 PTCK1 PTCK0
R/W R/W R/W
0 0 0
/4
SYS
SYS
/16
H
/64
H
SUB
SUB
and f are other internal clocks, the details of which can
H SUB
91
Bit
3 2 1
PTON — —
PTOC PTPOL PTCAPTS PTCCLR
D3 D2 D1
— — D9
D3 D2 D1
— — D9
PTRP3 PTRP2 PTRP1
— — PTRP9
3 2 1
PTON — —
R/W — —
0 — —
October 26, 2018
0
—
D0
D8
D0
D8
PTRP0
PTRP8
0
—
—
—
is
SYS