Watchdog Timer Operation - Holtek BS86DH12C Manual

BS86DH12C
High Voltage Touch A/D Flash MCU with HVIO
LRF: LVRC register software reset flag
Bit 1
Described elsewhere
Bit 0 WRF: WDTC register software reset flag
0: Not occurred
1: Occurred
This bit is set high by the WDTC register software reset and cleared to zero by the
application program. Note that this bit can only be cleared to zero by the application
program.

Watchdog Timer Operation

The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear instruction will not be executed in the
correct manner, in which case the Watchdog Timer will overflow and reset the device. There are five
bits, WE4~WE0, in the WDTC register to offer the enable control and reset control of the Watchdog
Timer. The WDT function will be enabled if the WE4~WE0 bits are equal to 10101B or 01010B.
If the WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the
device after a delay time, t
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the STATUS register will be set and only the Program Counter and
Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog
Timer. The first is a WDTC register software reset, which means a certain value except 01010B and
10101B written into the WE4~WE0 bits, the second is using the Watchdog Timer software clear
instruction and the third is via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single "CLR WDT" instruction to clear the WDT.
The maximum time-out period is when the 2
32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8s
for the 2 division ratio, and a minimum timeout of 8ms for the 2
18
WDTC Register
"CLR WDT" Instruction
"HALT" Instruction
Rev. 1.00
. After power on these bits will have a value of 01010B.
SRESET
WE4~WE0 Bits
01010B or 10101B
Any other value
Watchdog Timer Enable/Reset Control
18
WE4~WE0 bits
f
LIRC
LIRC 8-stage Divider
WS2~WS0
Watchdog Timer
55
WDT Function
Enable
Reset MCU
division ratio is selected. As an example, with a
division ration.
8
Reset MCU
CLR
8
f /2
LIRC
WDT Prescaler
8-to-1 MUX
WDT Time-out
8 18
(2 /f ~ 2 /f )
LIRC LIRC
October 26, 2018