Holtek BS86DH12C Manual page 132

I C Control Registers
2
There are three control registers for the I
is used to control the enable/disable function and to set the data transmission clock frequency.
The IICC1 register contains the relevant flags which are used to indicate the I
status. Another register, IICTOC, is used to control the I
corresponding section.
• IICC0 Register
Bit 7
Name —
R/W —
POR —
Bit 7~4 Unimplemented, read as "0"
Bit 3~2 IICDEB1~IICDEB0: I
00: No debounce
01: 2 system clock debounce
1x: 4 system clock debounce
Note that the I
derived from the f
circuit will have no effect and be bypassed.
Bit 1 IICEN: I
0: Disable
1: Enable
The bit is the overall on/off control for the I
to zero to disable the I
and the I
high the I
the I
the contents of the I
settings and should therefore be first initialised by the application program while the
relevant I
default states.
Bit 0 Unimplemented, read as "0"
• IICC1 Register
Bit 7
Name HCF
R/W R
POR 1
HCF: I
Bit 7
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCF flag is the data transfer flag. This flag will be zero when data is being
transferred. Upon completion of an 8-bit data transfer the flag will go high and an
interrupt will be generated.
Bit 6 HAAS: I
0: Not address match
1: Address match
The HAAS flag is the address match flag. This flag is used to determine if the slave
device address is the same as the master transmit address. If the addresses match then
this bit will be high, if there is no match then the flag will be low.
Rev. 1.00
High Voltage Touch A/D Flash MCU with HVIO
C interface, IICC0, IICC1 and IICTOC. The IICC0 register
2
6 5
— —
— —
— —
C Debounce Time Selection
2
C debounce circuit will operate normally if the system clock, f
2
clock or the IAMWU bit is equal to 0. Otherwise, the debounce
H
C Enable Control
2
C interface, the SDA and SCL lines will lose their I
2
C operating current will be reduced to a minimum value. When the bit is
2
C interface is enabled. The I
2
C interface for this bit to be effective. If the IICEN bit changes from low to high,
2
C control bits such as HTX and TXAK will remain at the previous
2
C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their
2
6 5
HAAS HBB HTX
R R R/W
0 0
C Bus data transfer completion flag
2
C Bus address match flag
2
132
C time-out function and is described in the
2
4 3 2
— IICDEB1 IICDEB0
— R/W R/W
— 0 0
C interface. When the IICEN bit is cleared
2
C configuration option must have first enabled
2
4 3 2
TXAK SRW
R/W R
0 0 0
BS86DH12C
C communication
2
1 0
IICEN —
R/W —
0 —
, is
SYS
C function
2
1 0
IAMWU RXAK
R/W R
0 1
October 26, 2018