Holtek BS86DH12C Manual page 48

• HIRCC Register
Bit 7
Name —
R/W —
POR —
Bit 7~4 Unimplemented, read as "0"
HIRC1~HIRC0: HIRC frequency selection
Bit 3~2
00: 8MHz
01: 12MHz
10: 16MHz
11: 8MHz
When the HIRC oscillator is enabled or the HIRC frequency selection is changed
by application program, the clock frequency will automatically be changed after the
HIRCF flag is set to 1.
It is recommended that the HIRC frequency selected by these two bits should be the
same with the frequency determined by the configuration option to achieve the HIRC
frequency accuracy specified in the A.C. Characteristics.
HIRCF: HIRC oscillator stable flag
Bit 1
0: Unstable
1: Stable
This bit is used to indicate whether the HIRC oscillator is stable or not. When the
HIRCEN bit is set to 1 to enable the HIRC oscillator, the HIRCF bit will first be
cleared to 0 and then set to 1 after the HIRC oscillator is stable.
Bit 0 HIRCEN: HIRC oscillator enable control
0: Disable
1: Enable
• LXTC Register
Bit 7
Name —
R/W —
POR —
Bit 7~3 Unimplemented, read as "0"
LXTSP: LXT oscillator quick start control
Bit 2
0: Disable – Low Power
1: Enable – Quick Start
This bit is used to control whether the LXT oscillator is operating in the low power
or quick start mode. When the LXTSP bit is set to 1, the LXT oscillator will oscillate
quickly but consume more power. If the LXTSP bit is cleared to 0, the LXT oscillator
will consume less power but take longer time to stablise. It is important to note that
this bit can not be changed after the LXT oscillator is selected as the system clock
source using the CKS2~CKS0 and FSS bits in the SCC register.
LXTF: LXT oscillator stable flag
Bit 1
0: Unstable
1: Stable
This bit is used to indicate whether the LXT oscillator is stable or not. When the
LXTEN bit is set to 1 to enable the LXT oscillator, the LXTF bit will first be cleared
to 0 and then set to 1 after the LXT oscillator is stable.
Bit 0 LXTEN: LXT oscillator enable control
0: Disable
1: Enable
Rev. 1.00
High Voltage Touch A/D Flash MCU with HVIO
6 5 4
— — —
— — —
— — —
6 5 4
— — —
— — —
— — —
48
BS86DH12C
3 2 1
HIRC1 HIRC0 HIRCF
R/W R/W R
0 0 0
3 2 1
— LXTSP LXTF
— R/W R
— 0 0
October 26, 2018
0
HIRCEN
R/W
1
0
LXTEN
R/W
0