Holtek BS86DH12C Manual page 134

data transfer completion or from the I
after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/
write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to
determine whether to go into transmit or receive mode. Before any transfer of data to or from the I
bus, the microcontroller must initialise the bus, the following are steps to achieve this:
• Step 1
Set the IICEN bit in the IICC0 register to "1" to enable the I
• Step 2
Write the slave address of the device to the I
• Step 3
Set the IICE interrupt enable bit of the interrupt control register to enable the I
I C Bus Start Signal
2
The START signal can only be generated by the master device connected to the I
the slave device. This START signal will be detected by all devices connected to the I
detected, this indicates that the I
condition occurs when a high to low transition on the SDA line takes place when the SCL line
remains high.
I C Slave Address
2
The transmission of a START signal by the master will be detected by all devices on the I
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines
the read/write status and will be saved to the SRW bit of the IICC1 register. The slave device will
then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set
the status flag HAAS when the addresses match.
Rev. 1.00
High Voltage Touch A/D Flash MCU with HVIO
C bus time-out occurrence. During a data transfer, note that
2
C bus address register IICA.
2
Start
SET IICEN
Write Slave
Address to IICA
No
2
I C Bus
Interrupt=?
CLR IICE
Poll IICF to decide
2
when to go to I C Bus ISR
Go to Main Program
I 2 C Bus Initialisation Flowchart
C bus is busy and therefore the HBB bit will be set. A START
2
134
BS86DH12C
C bus.
2
C interrupt.
2
Yes
SET IICE
Wait for Interrupt
Go to Main Program
C bus and not by
2
C bus. When
2
October 26, 2018
C
2
C bus.
2
C bus
2