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Holtek BS67F340 Manual

Enhanced touch a/d flash mcu with lcd driver
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Enhanced Touch A/D Flash MCU with LCD Driver
BS67F340/BS67F350
BS67F360/BS67F370
Revision: V1.40
Date: De�e��e� 1�� �01�
De�e��e� 1�� �01�

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Summary of Contents for Holtek BS67F340

  • Page 1 Enhanced Touch A/D Flash MCU with LCD Driver BS67F340/BS67F350 BS67F360/BS67F370 Revision: V1.40 Date: De�e��e� 1�� �01� De�e��e� 1�� �01�...

  • Page 2: Table Of Contents

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Table of Contents Features ........................ 7 CPU Featu�es ..........................7 Pe�iphe�al Featu�es ........................8 General Description ..................... 9 Selection Table ..................... 9 Block Diagram ....................10 Pin Assignment ....................10 Pin Descriptions ....................18 Absolute Maximum Ratings ................
  • Page 3 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Special Function Register Description ............69 Indirect Addressing Registers − IAR0, IAR1, IAR2 ..............�9 Memory Pointers − MP0, MP1H/MP1L, MP2H/MP2L ..............�9 P�og�a� Me�o�y Bank Pointe� – PBP ..................71 Accumulator − ACC ........................71 Program Counter Low Register −...
  • Page 4 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Input/Output Ports ................... 104 Pull-high Resisto�s ........................107 Po�t A Wake-up ........................107 I/O Port Control Registers ......................107 Pin-sha�ed Fun�tions .......................108 I/O Pin Structures ........................1�1 P�og�a��ing Conside�ations ....................1�� Timer Modules – TM ..................122 Int�odu�tion ..........................1��...
  • Page 5 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver UART Interface ....................195 UART Exte�nal Pin ........................19� UART Data T�ansfe� S�he�e....................19� UART Status and Cont�ol Registe�s..................19� Baud Rate Gene�ato� .......................�0� UART Setup and Cont�ol......................�03 UART T�ans�itte�........................�04 UART Re�eive� ........................�0� Managing Re�eive� E��o�s .......................�07 UART Inte��upt St�u�tu�e......................�08...
  • Page 6 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Application Circuits ..................254 Instruction Set ....................255 Int�odu�tion ..........................��� Inst�u�tion Ti�ing ........................��� Moving and T�ansfe��ing Data ....................��� A�ith�eti� Ope�ations .......................��� Logi�al and Rotate Ope�ation ....................��� B�an�hes and Cont�ol T�ansfe� ....................���...

  • Page 7: Features

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Features CPU Features • Operating voltage = 8MHz: 2.2V~5.5V ♦ = 12MHz: 2.7V~5.5V ♦ = 16MHz: 3.3V~5.5V ♦ • Up to 0.25μs instruction cycle with 16MHz system clock at V • Power down and wake-up functions to reduce power consumption • Oscillator type External High Speed Crystal – HXT ♦ Internal High Speed RC – HIRC ♦ External 32.768kHz Crystal – LXT ♦ Internal 32kHz RC – LIRC ♦ • Fully integrated internal 8/12/16MHz oscillator requires no external components • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one to three instruction cycles • Table read instructions...
  • Page 8 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Peripheral Features • Program Memory: Up to 32K×16 • Data Memory: Up to 1536×8 • True EEPROM Memory: 128×8 • Watchdog Timer function • Up to 59 bidirectional I/O lines • Two external interrupt lines shared with I/O pins • Multiple Timer Modules for time measure, input capture, compare match output, PWM output function or single pulse output function • Serial Interfaces Module – SIM for SPI or I • Fully-duplex Universal Asynchronous Receiver and Transmitter Interface – UART • LCD driver funciton with 1/3 bias – R-type & C-type bias • Fully integrated up to 36 touch key functions – require no external components • Dual Time-Base functions for generation of fixed time interrupt signals • 8-channel 12-bit resolution A/D converter • Temperature Sensor • In Application Programming function – IAP...

  • Page 9: General Description

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver General Description The series of devices are Flash Memory A/D type 8-bit high performance RISC architecture microcontroller with fully integrated touch key functions. With all touch key functions provided internally and with the convenience of Flash Memory multi-programming features, each device has all the features to offer designers a reliable and easy means of implementing Touch Keyes within their products applications. The touch key functions are fully integrated completely eliminating the need for external components. In addition to the flash program memory, other memory includes an area of RAM Data...

  • Page 10: Block Diagram

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Block Diagram Reset Inte�nal Wat�hdog Ci��uit HIRC/LIRC Ti�e� Os�illato�s Inte��upt Cont�olle� 8-�it Flash/EEPROM P�og�a��ing Ci��uit�y RISC External HXT Voltage Voltage Co�e Os�illato� Dete�t Reset External LXT EEPROM Flash RAM Data Ti�e Os�illato�...
  • Page 11 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver 4� 4� 4� PB4/PTPB/PTPI/AN4/KEY1 3� 3� PB5/STCK/AN5/KEY2 � PA1/CTP0/V2 PB6/PTCK/AN6/KEY3 PA5/CTP0B/C1 PB7/INT1/AN7/KEY4 PA6/CTCK0/INT0/C2 SEG0/PD0/KEY13 � 3� COM0 BS67F350/BS67V350 SEG1/PD1/KEY14 � COM1 48 LQFP-A SEG2/PD2/KEY15 COM� SEG3/PD3/KEY16 �9 COM3 SEG4/PD4/KEY17 �8 SEG�7 SEG5/PD5/KEY18 �7...
  • Page 12 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver �4 �3 �� �1 �0 �9 �8 �7 �� �� �4 �3 �� �1 �0 PC0/KEY5 � PA1/CTP0/V2 PC1/KEY6 4� PA5/CTP0B/C1 PC2/KEY7 4� PA6/CTCK0/INT0/C2 PC3/KEY8 � PC4/KEY9 COM0 � COM1 PC5/KEY10 4�...
  • Page 13 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver 4� 4� 4� 3� PB4/PTPB/PTPI/AN4/KEY1 PB5/STCK/AN5/KEY2 � 3� PA1/CTP0/V2 PB6/PTCK/AN6/KEY3 PA5/CTP0B/C1 PB7/INT1/AN7/KEY4 PA6/CTCK0/INT0/C2 SEG8/PD0/KEY13 � 3� COM0 BS67F360/BS67V360 SEG9/PD1/KEY14 � COM1 48 LQFP-A SEG10/PD2/KEY15 COM� SEG11/PD3/KEY16 �9 COM3 SEG12/PD4/KEY17 �8 SEG3�...
  • Page 14 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver �1 �0 �4 �3 �� �1 �0 �9 �8 �7 �� �� �4 �3 �� SEG0/PC0/KEY5 � PA1/CTP0/V2 SEG1/PC1/KEY6 4� PA5/CTP0B/C1 SEG2/PC2/KEY7 4� PA6/CTCK0/INT0/C2 SEG3/PC3/KEY8 � SEG4/PC4/KEY9 COM0 � SEG5/PC5/KEY10 COM1 4�...
  • Page 15 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver 4� 4� 4� 3� PB4/PTPB/PTPI/AN4/KEY1 PB5/STCK/AN5/KEY2 � 3� PA1/CTP0/V2 PB6/PTCK/AN6/KEY3 PA5/CTP0B/C1 PB7/INT1/AN7/KEY4 PA6/CTCK0/INT0/C2 SEG8/PD0/KEY13 � 3� COM0 BS67F370/BS67V370 SEG9/PD1/KEY14 � COM1 48 LQFP-A SEG10/PD2/KEY15 COM� SEG11/PD3/KEY16 �9 COM3 SEG12/PD4/KEY17 �8 SEG3�...
  • Page 16 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver �1 �0 �4 �3 �� �1 �0 �9 �8 �7 �� �� �4 �3 �� SEG0/PC0/KEY5 � PA1/CTP0/V2 SEG1/PC1/KEY6 4� PA5/CTP0B/C1 SEG2/PC2/KEY7 4� PA6/CTCK0/INT0/C2 SEG3/PC3/KEY8 � SEG4/PC4/KEY9 COM0 � SEG5/PC5/KEY10 COM1 4�...
  • Page 17 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver 80 79 78 77 7� 7� 74 73 7� 71 70 �9 �8 �7 �� �� �4�3 �� �1 PB4/PTPB/PTPI/AN4/KEY1 �0 PA1/CTP0/V2 PB5/STCK/AN5/KEY2 � �9 PA5/CTP0B/C1 PB6/PTCK/AN6/KEY3 �8 PB7/INT1/AN7/KEY4 PA6/CTCK0/INT0/C2 �7 COM0 �...

  • Page 18: Pin Descriptions

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pin Descriptions With the exception of the power pins and some relevant transformer control pins, all pins on these devices can be referenced by their Port name, e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. As the Pin Description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. BS67F340 Pad Name Function Description PAWU General purpose I/O. Register enabled pull-up PAPU CMOS and wake-up. PAS0 PA0/SDO/ICPDA/OCDSDA PAS0 — CMOS SPI data output ICPDA —...
  • Page 19 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PAWU General purpose I/O. Register enabled pull-up PAPU CMOS and wake-up. PAS1 PA7/KEY12/SEG7 KEY12 PAS1 — Tou�h key input SEG7 PAS1 — LCD seg�ent output PBPU CMOS General purpose I/O. Register enabled pull-up.
  • Page 20 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PCPU CMOS General purpose I/O. Register enabled pull-up. PCS0 PC0/KEY5/SEG0 KEY5 PCS0 — Tou�h key input SEG0 PCS0 — LCD seg�ent output PCPU CMOS General purpose I/O. Register enabled pull-up.
  • Page 21 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PEPU CMOS General purpose I/O. Register enabled pull-up. PES1 PE4/KEY13/SEG8 KEY13 PES1 — Tou�h key input SEG8 PES1 — LCD seg�ent output PEPU PE� CMOS General purpose I/O. Register enabled pull-up.
  • Page 22 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver BS67F350 Pad Name Function Description PAWU General purpose I/O. Register enabled pull-up PAPU CMOS and wake-up. PAS0 PA0/SDO/ICPDA/OCDSDA PAS0 — CMOS SPI data output ICPDA — CMOS ICP Data/Address pin OCDSDA —...
  • Page 23 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PBPU CMOS General purpose I/O. Register enabled pull-up. PBS0 PBS0 — SPI data input PB0/SDI/SDA/VREF/AN0 PBS0 NMOS I � C data line VREF PBS0 — A/D Converter reference voltage output PBS0 —...
  • Page 24 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PCPU CMOS General purpose I/O. Register enabled pull-up. PCS0 PC1/KEY6 KEY6 PCS0 — Tou�h key input PCPU PC� CMOS General purpose I/O. Register enabled pull-up. PCS0 PC2/KEY7...
  • Page 25 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PEPU CMOS General purpose I/O. Register enabled pull-up. PES0 PE0/SEG8 SEG8 PES0 — LCD seg�ent output PEPU CMOS General purpose I/O. Register enabled pull-up. PES0 PE1/OSC1/SEG9 OSC1 PES0 —...
  • Page 26 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver BS67F360 Pad Name Function Description PAWU General purpose I/O. Register enabled pull-up PAPU CMOS and wake-up. PAS0 PA0/SDO/ICPDA/OCDSDA PAS0 — CMOS SPI data output ICPDA — CMOS ICP Data/Address pin OCDSDA —...
  • Page 27 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PBPU CMOS General purpose I/O. Register enabled pull-up. PBS0 PBS0 — SPI data input PB0/SDI/SDA/VREF/AN0 PBS0 NMOS I � C data line VREF PBS0 — A/D Converter reference voltage output PBS0 —...
  • Page 28 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PCPU CMOS General purpose I/O. Register enabled pull-up. PCS0 PC1/KEY6/SEG1 KEY6 PCS0 — Tou�h key input SEG1 PCS0 — LCD seg�ent output PCPU PC� CMOS General purpose I/O. Register enabled pull-up.
  • Page 29 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PDPU PD� CMOS General purpose I/O. Register enabled pull-up. PDS1 PD5/KEY18/SEG13 KEY18 PDS1 — Tou�h key input SEG13 PDS1 — LCD seg�ent output PDPU PD� CMOS General purpose I/O. Register enabled pull-up.
  • Page 30 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PFPU CMOS General purpose I/O. Register enabled pull-up. PFS0 PF0/OSC1/SEG28 OSC1 PFS0 — HXT oscillator pin SEG�8 PFS0 — LCD seg�ent output PFPU CMOS General purpose I/O. Register enabled pull-up.
  • Page 31 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver BS67F370 Pad Name Function Description PAWU General purpose I/O. Register enabled pull-up PAPU CMOS and wake-up. PAS0 PA0/SDO/ICPDA/OCDSDA PAS0 — CMOS SPI data output ICPDA — CMOS ICP Data/Address pin OCDSDA —...
  • Page 32 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PBPU CMOS General purpose I/O. Register enabled pull-up. PBS0 PBS0 — SPI data input PB0/SDI/SDA/VREF/AN0 PBS0 NMOS I C data line � VREF PBS0 — A/D Converter reference voltage output PBS0 —...
  • Page 33 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PCPU CMOS General purpose I/O. Register enabled pull-up. PCS0 PC1/KEY6/SEG1 KEY6 PCS0 — Tou�h key input SEG1 PCS0 — LCD seg�ent output PCPU PC� CMOS General purpose I/O. Register enabled pull-up.
  • Page 34 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PDPU PD� CMOS General purpose I/O. Register enabled pull-up. PDS1 PD5/KEY18/SEG13 KEY18 PDS1 — Tou�h key input SEG13 PDS1 — LCD seg�ent output PDPU PD� CMOS General purpose I/O. Register enabled pull-up.
  • Page 35 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PFPU CMOS General purpose I/O. Register enabled pull-up. PFS0 PF0/OSC1/SEG28 OSC1 PFS0 — HXT oscillator pin SEG�8 PFS0 — LCD seg�ent output PFPU CMOS General purpose I/O. Register enabled pull-up.

  • Page 36: Absolute Maximum Ratings

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pad Name Function Description PHPU CMOS General purpose I/O. Register enabled pull-up. PHS0 PH3/SEG43 SEG43 PHS0 — LCD seg�ent output PHPU CMOS General purpose I/O. Register enabled pull-up. PHS1 PH4/SEG44 SEG44 PHS1 —...

  • Page 37: D.c. Characteristics

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver D.C. Characteristics Ta=��°C Test Conditions Symbol Parameter Min. Max. Unit Conditions =8MHz �.� — �.� Operating Voltage (HXT) — =12MHz �.7 — �.� =16MHz — �.� =8MHz �.� — �.� Operating Voltage (HIRC) —...

  • Page 38: A.c. Characteristics

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver A.C. Characteristics Ta=��°C Test Condition Symbol Parameter Min. Max. Unit Condition �.�V~�.�V f =8MHz — — System Clock (HXT) �.7V~�.�V f =12MHz — 1� — 3.3V~�.�V f =16MHz — 1� —...

  • Page 39: A/D Converter Characteristics

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Test Condition Symbol Parameter Min. Max. Unit Condition Syste� Reset Delay Ti�e (Powe�-on �eset� — — �� �0 �s LVR ha�dwa�e �eset� LVRC/WDTC/RSTC software reset) RSTD Syste� Reset Delay Ti�e —...

  • Page 40: Temperature Sensor Electrical Characteristics

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Temperature Sensor Electrical Characteristics Ta=25°C, Operating Temperature: -40°C~85°C, unless otherwise specified. Test Conditions Symbol Parameter Min. Max. Unit Conditions Ope�ating Voltage — — �.7 — �.� 3V Ta=��°C� T�i� @ V Te�pe�atu�e Senso�...

  • Page 41: Lcd Driver Electrical Characteristics

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LCD Driver Electrical Characteristics Ta=��°C Test Conditions Symbol Parameter Min. Max. Unit Conditions R type� powe� supply f�o� PLCD pin� — — �.� PLCD[3:0]=1xxxB — C type� powe� supply f�o� PLCD pin �.0...
  • Page 42 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Touch Key RC Oscillator 1000kHz Mode Selected Test Conditions Symbol Parameter Min. Max. Unit Conditions — Only Sensor (KEY) Oscillator Operating =1000kHz μA KEYOSC SENOSC Cu��ent �V — 1�0 — =1000kHz, MnTSS=0 μA...

  • Page 43: Power-On Reset Characteristics

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Touch Key RC Oscillator 2000kHz mode selected Test Conditions Symbol Parameter Min. Max. Unit Conditions — 1�0 Only Sensor (KEY) Oscillator Operating =2000kHz μA KEYOSC SENOSC Cu��ent �V — 1�0 3�0 —...

  • Page 44: System Architecture

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one or two cycles for most of the standard or extended instructions respectively, with the exception of branch or call instructions which need one more cycle. An 8-bit wide ALU is used in practically all instruction set...
  • Page 45 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver F e t c h I n s t . 1 E x e c u t e I n s t . 1 M O V A , [ 1 2 H ] C A L L D E L A Y F e t c h I n s t .

  • Page 46: P�Og�A� Counte

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P�og�a� Counte� Top of Sta�k Sta�k Level 1 Sta�k Level � Sta�k Sta�k Level 3 Pointe�...

  • Page 47: Flash Program Memory

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Flash Program Memory The Program Memory is the location where the user code or program is stored. For these devices series the Program Memory are Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Device Capacity Banks BS�7F340 4K × 1�...

  • Page 48: Look-Up Ta�Le

    ORG statement. The value at this ORG statement is “0F00H” which refers to the start address of the last page within the 4K Program Memory of the BS67F340. The table pointer low byte register is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “0F06H” or 6 locations after the start of the last page. Note that the value for the table pointer...

  • Page 49: In Ci

    In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re- insertion of the device. Holtek Writer Pins MCU Programming Pins Pin Description ICPDA Programming Serial Data/Address ICPCK PA� P�og�a��ing Clo�k Powe� Supply G�ound...
  • Page 50 BS67F3x0. The EV chip device also provides the “On-Chip Debug” function to debug the real MCU device during development process. The EV chip and real MCU devices, BS67V3x0 and BS67F3x0, are almost functional compatible except the “On-Chip Debug” function. Users can use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip device for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Holtek e-Link Pins EV Chip OCDS Pins Pin Description OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output OCDSCK OCDSCK On-Chip De�ug Suppo�t Clo�k input Powe� Supply G�ound In Application Programming – IAP These devices offer IAP function to update data or application program to flash ROM. Users can...
  • Page 51 FRDEN D� D� D� FC� — — — — — — — CLWB (BS67F350/360/370) FARL A� A� A� FARH (BS67F340) — — — — FARH (BS67F350) — — — A1� FARH (BS67F360) — — A1� FARH (BS67F370) — A1� FD0L D�...
  • Page 52 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • FC0 Register Name CFWEN FMOD� FMOD1 FMOD0 FWPEN FRDEN Bit 7 CFWEN: Flash Memory Write enable control 0: Flash memory write function is disabled 1: Flash memory write function has been successfully enabled When this bit is cleared to 0 by application program, the Flash memory write function is disabled. Note that writing a “1” into this bit results in no action. This bit is used to indicate that the Flash memory write function status. When this bit is set to 1 by hardware, it means that the Flash memory write function is enabled successfully. Otherwise, the Flash memory write function is disabled as the bit content is zero. Bit 6~4 FMOD2~FMOD0: Mode selection 000: Write program memory 001: Block/Page erase program memory 010: Reserved 011: Read program memory 10x: Reserved 110: FWEN mode – Flash memory Write function Enabled mode...
  • Page 53 1: Initiate Write Buffer Clear process This bit is set by software and cleared by hardware when the Write Buffer Clear process is completed. • FARL Register Name A� A� A� Bit 7~0 Flash Memory Address bit 7 ~ bit 0 • FARH Register – BS67F340 Name — — — — — — — — —...
  • Page 54 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • FARH Register – BS67F360 Name — — A1� — — — — Bit 7~6 Unimplemented, read as 0. Bit 5~0 Flash Memory Address bit 13 ~ bit 8 • FARH Register – BS67F370 Name — A1� — — Bit 7 Unimplemented, read as 0. Bit 6~0 Flash Memory Address bit 14 ~ bit 8 •...
  • Page 55 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • FD2L Register Name D� D� D� Bit 7~0 The third Flash Memory data bit 7 ~ bit 0 • FD2H Register Name D1� D1� Bit 7~0 The third Flash Memory data bit 15 ~ bit 8 • FD3L Register Name D� D� D� Bit 7~0 The fourth Flash Memory data bit 7 ~ bit 0 • FD3H Register Name D1�...
  • Page 56 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Flash Memory Write Function Enable Procedure In order to allow users to change the Flash memory data through the IAP control registers, users must first enable the Flash memory write operation by the following procedure: 1. Write “110” into the FMOD2~FMOD0 bits to select the FWEN mode. 2. Set the FWPEN bit to “1”. The step 1 and step 2 can be executed simultaneously. 3. The pattern data with a sequence of 00H, 04H, 0DH, 09H, C3H and 40H must be written into the FD1L, FD1H, FD2L, FD2H, FD3L and FD3H registers respectively. 4. A counter with a time-out period of 300μs will be activated to allow users writing the correct pattern data into the FD1L/FD1H ~ FD3L/FD3H register pairs. The counter clock is derived from LIRC oscillator. 5. If the counter overflows or the pattern data is incorrect, the Flash memory write operation will not be enabled and users must again repeat the above procedure. Then the FWPEN bit will automatically be cleared to 0 by hardware.
  • Page 57 1001 xxxx xxxx 1010 xxxx xxxx 1011 xxxx xxxx 1� 1100 xxxx xxxx 1101 xxxx xxxx 1110 xxxx xxxx 1� 1111 xxxx xxxx “x”: don’t �a�e BS67F340 Erase Block Number and Selection Rev. 1.40 �7 De�e��e� 1�� �01�...
  • Page 58 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Erase Page FARH FARL [7:5] FARL [4:0] 0000 0000 x xxxx 0000 0000 x xxxx � 0000 0000 x xxxx 0000 0000 x xxxx 0000 0000 x xxxx � 0000 0000 x xxxx �...
  • Page 59 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Page Eerase FARH FARL[7:6] FARL[5:0] 0000 0000 xx xxxx 0000 0000 xx xxxx � 0000 0000 xx xxxx 0000 0000 xx xxxx 0000 0001 xx xxxx � 0000 0001 xx xxxx 1��...
  • Page 60 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Read Flash Me�o�y Set FMOD [�:0]=011 & FRDEN=1 Set Flash Add�ess �egiste�s FARH=xxh, FARL=xxh Set FRD=1 FRD=0 ? Read data value: FD0L=xxh, FD0H=xxh Read Finish ? Clear FRDEN bit Read Flash Memory Procedure Rev.
  • Page 61 Set FMOD [�:0]=000 Sele�t “W�ite Flash Mode” Set W�ite sta�ting address: FARH/FARL W�ite data to data �egiste�: FD0L/FD0H, FD1L/FD1H, FD2L/FD2H, FD3L/FD3H, Set FWT=1 FWT=0 ? W�ite Finish ? Clear CFWEN=0 Write Flash Memory Procedure – BS67F340 Rev. 1.40 �1 De�e��e� 1�� �01�...
  • Page 62 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver W�ite Flash Me�o�y Flash Me�o�y W�ite Fun�tion Ena�le P�o�edu�e Set Page Erase address: FARH/FARL Set FMOD [�:0]=001 & FWT=1 Sele�t “Page E�ase �ode” & Initiate w�ite ope�ation FWT=0 ? Set FMOD [�:0]=000 Sele�t “W�ite Flash Mode”...

  • Page 63: Data Memory

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Data Memory The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two types, the first of Data Memory is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control.

  • Page 64: Data Me�O�Y Add�Essing

    Data Me�o�y (Se�to� �~Se�to� �) Gene�al Pu�pose Data Me�o�y (Sector 0 ~ Sector N) Se�to� 0 Se�to� 1 Sector N Note: N=3 for BS67F340; N=5 for BS67F350; N=7 for BS67F360; N=11 for BS67F370; Data Memory Structure Data Memory Addressing For these devices that support the extended instructions, there is no Bank Pointer for Data Memory. The Bank Pointer, PBP, is only available for Program Memory. For Data Memory the desired Sector is pointed by the MP1H or MP2H register and the certain Data Memory address in the selected sector is specified by the MP1L or MP2L register when using indirect addressing access.
  • Page 65 7�H PEPU TB0C TB1C 3�H SIMTOC 7�H 3�H SIMC0 7�H SIMC1 UCR1 SIMD UCR� SIMA/SIMC� TXR_RXR CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL : Unused� �ead as 00H CTM0AH Special Purpose Data Memory Structure – BS67F340 Rev. 1.40 �� De�e��e� 1�� �01�...
  • Page 66 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Se�to� 0 Se�to� 1 Se�to� 0 Se�to� 1 IAR0 TKTMR TKC0 0�H IAR1 TK1�DL 4�H MP1L TK1�DH MP1H TKC1 PSCR1 0�H TKM01�DL 4�H PAS0 0�H TKM01�DH 4�H LCDC0 PAS1 TBLP TKM0ROL...
  • Page 67 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Se�to� 0 Se�to� 1 Se�to� 0 Se�to� 1 IAR0 TKTMR TKC0 0�H IAR1 TK1�DL 4�H MP1L TK1�DH MP1H TKC1 PSCR1 0�H TKM01�DL 4�H PAS0 0�H TKM01�DH 4�H LCDC0 PAS1 TBLP TKM0ROL...
  • Page 68 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Se�to� 0 Se�to� 1 Se�to� 0 Se�to� 1 IAR0 TKTMR TKC0 0�H IAR1 TK1�DL 4�H MP1L TK1�DH MP1H TKC1 PSCR1 0�H TKM01�DL 4�H PAS0 0�H TKM01�DH 4�H LCDC0 PAS1 TBLP TKM0ROL...

  • Page 69: Special Function Register Description

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section. However, several registers require a separate description in this section. Indirect Addressing Registers − IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with MP2L/MP2H register pair can access data from any Data Memory sector. As...
  • Page 70 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Example 2 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ‘code’ org 00h start: mov a,04h ; setup size of block...

  • Page 71: Accumulator − Acc

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Program Memory Bank Pointer – PBP For the BS67F360/BS67F370 devices the Program Memory is divided into several banks. Selecting the required Program Memory area is achieved using the Program Memory Bank Pointer, PBP. The PBP register should be properly configured before the device executes the “Branch” operation using the “JMP” or “CALL” instruction. After that a jump to a non-consecutive Program Memory address which is located in a certain bank selected by the program memory bank pointer bits will occur. PBP Register – BS67F360 Name D� D� D� PBP0 Bit 7~1 D7~D1: General data bits and can be read or written. PBP0: Program Memory Bank Point bit 0 Bit 0 0: Bank 0 1: Bank 1 PBP Register – BS67F370 Name D�...

  • Page 72: Look-Up Table Registers - Tblp, Tbhp, Tblh

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register − STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/ logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through...
  • Page 73 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver STATUS Register Name “x”: unknown Bit 7 SC: The result of the “XOR” operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6 CZ: The the operational result of different flags for different instuctions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/ SBCM/ LSBC/ LSBCM instructions, the CZ flag is the “AND” operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag willl not be affected. Bit 5 TO: Watchdog Time-out flag 0: After power up ow executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred Bit 4 PDF: Power down flag 0: After power up ow executing the “CLR WDT” instruction 1: By executing the “HALT” instructin Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero...

  • Page 74: Eeprom Data Memory

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver EEPROM Data Memory These devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product...
  • Page 75 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver EED Register Name D� D� D� Bit 7~0 D7~D0: Data EEPROM data bit 7~bit0 EEC Register Name — — — — WREN RDEN — — — — — — — — Bit 7~4 Unimplemented, read as 0. WREN: Data EEPROM write enable Bit 3 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data...

  • Page 76: Reading Data F�O� The Eeprom

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. Then the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the...
  • Page 77 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory Pointer high byte register could be normally cleared to zero as this would inhibit access to sector 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Example Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, 040H ;...

  • Page 78: Oscillators

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Oscillators Various oscillator types offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of application program and relevant control registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through register programming. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, each device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Frequency Pins External High Speed Crystal 400kHz~16MHz OSC1/OSC2 Internal High Speed RC...

  • Page 79: External Crystal/Ceramic Oscillator − Hxt

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver High Speed Os�illato�s HIRC HIRCEN P�es�ale� HXTEN Low Speed Os�illato�s CKS�~CKS0 LXTEN LIRC LIRC LIRC System Clock Configurations External Crystal/Ceramic Oscillator − HXT The External Crystal/Ceramic System Oscillator is the high frequency oscillator, which is the default oscillator clock source after power on. For most crystal oscillator configurations, the simple...

  • Page 80: Internal High Speed Rc Oscillator − Hirc

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Internal High Speed RC Oscillator − HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8/12/16 MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 3V or 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 12MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/ O pins are free for use as normal I/O pins. External 32.768 kHz Crystal Oscillator − LXT The External 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices,...

  • Page 81: Internal 32Khz Oscillator − Lirc

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. I n t e r n a l X T 1 O s c i l l a t o r C i r c u i t I n t e r n a l R C 3 2 .

  • Page 82: Operating Modes And System Clocks

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks Each device has different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock selections using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, f , or low frequency, f , source, and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is sourced from an HXT or HIRC oscillator, selected via configuring the FHS bit in the SCC register. The low speed system clock source can be sourced from the internal clock f . If f is selected then it can be sourced by either the LXT or LIRC oscillators, selected via configuring the FSS bit in the SCC register. The other choice, which is a divided version of the high speed system oscillator has a range of f /2~f /64. High Speed Os�illato�s...

  • Page 83: Syste� Ope�Ation Modes

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the...
  • Page 84 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral functions. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU will be switched off but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. IDLE2 Mode The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. Control Registers The registers, SCC, HIRCC, HXTC and LXTC, are used to control the system clock and the corresponding oscillator configurations.
  • Page 85 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver FSS: Low Frequency clock selection Bit 2 0: LIRC 1: LXT FHIDEN: High Frequency oscillator control when CPU is switched off Bit 1 0: Disable 1: Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an “HALT” instruction. FSIDEN: Low Frequency oscillator control when CPU is switched off Bit 0 0: Disable 1: Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an “HALT” instruction. The LIRC oscillator is controlled by this bit together with the WDT function enable control when the LIRC is selected to be the low speed oscillator clock source or the WDT function is enabled respectively. If this bit is cleared to 0 but the WDT function is enabled, the LIRC oscillator will also be enabled.
  • Page 86 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver HXTC Register Name — — — — — HXTM HXTF HXTEN — — — — — — — — — — Bit 7~3 Unimplemented, read as 0. HXTM: HXT mode selection Bit 2 0: HXT frequency ≤ 10 MHz 1: HXT frequency >10 MHz This bit is used to select the HXT oscillator operating mode. Note that this bit must be properly configured before the HXT is enabled. When the HXTEN bit is set to 1 to enable the HXT oscillator, it is invalid to change the value of this bit. Bit 1...
  • Page 87 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Operating Mode Switching These devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the CKS2~CKS0 bits in the SCC register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register. NORMAL SLOW /�4 CPU �un CPU �un on/off SLEEP IDLE0 HALT instruction executed...
  • Page 88 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the CKS2~CKS0 bits to “111” in the SCC register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC register and therefore requires this oscillator to be stable before full mode switching occurs. NORMAL Mode CKS�~CKS0 = 111...
  • Page 89 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver SLOW Mode to NORMAL Mode Switching In SLOW mode the system clock is derived from f . When system clock is switched back to the NORMAL mode from f , the CKS2~CKS0 bits should be set to “000” ~“110” and then the system clock will respectively be switched to f /64. However, if f is not used in SLOW mode and thus switched off, it will take some time to re- oscillate and stabilise when switching to the NORMAL mode from the SLOW Mode. This is monitored using the HXTF bit in the HXTC register or the HIRCF bit in the HIRCC register. The time duration required for the high speed system oscillator stabilization is specified in the A.C.
  • Page 90 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the FHIDEN bit in the SCC register equal to “0” and the FSIDEN bit in the SCC register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The f clock will be stopped and the application program will stop at the “HALT” instruction, but the f clock will be on. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting as the WDT function is always enabled. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The f and f clocks will be on but the application program will stop at the “HALT” instruction.

  • Page 91: Wake-Up

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator has enabled. In the IDLE1 and IDLE 2 Mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow When the device executes the “HALT” instruction, the PDF flag will be set to 1. The PDF flag will...

  • Page 92: Watchdog Timer

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal RC oscillator, f . The LIRC internal LIRC oscillator has an approximate frequency of 32 kHz and this specified internal clock period can vary with V , temperature and process variations. The Watchdog Timer source clock is then subdivided by a ratio of 2 to 2 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register controls the overall operation of the Watchdog Timer.
  • Page 93 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver RSTFC Register Name — — — — RSTF LVRF — — — — — — — — “x”: unknown Bit 7~4 Unimplemented, read as “0” Bit 3 RSTF: Reset control register software reset flag Described elsewhere. Bit 2 LVRF: LVR function reset flag Described elsewhere. LRF: LVR control register software reset flag Bit 1 Described elsewhere. Bit 0...

  • Page 94: Reset And Initialisation

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver WDTC WE4~WE0 �its Reset MCU Registe� “HALT”Inst�u�tion “CLR WDT”Inst�u�tion /� LIRC LIRC LIRC 8-stage Divide� WDT P�es�ale� WS�~WS0 8-to-1 MUX WDT Ti�e-out /� /� (� ~ � LIRC LIRC LIRC LIRC...
  • Page 95 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Internal Reset Control There is an internal reset control register, RSTC, which is used to provide a reset when the device operates abnormally due to the environmental noise interference. If the content of the RSTC register is set to any value other than 01010101B or 10101010B, it will reset the device after 2~3 f clock LIRC cycles. After power on the register will have a value of 01010101B. RSTC7 ~ RSTC0 Bits Reset Function 01010101B No operation 10101010B No operation Any othe� value Reset MCU Internal Reset Function Control • RSTC Register...
  • Page 96 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage, V . If the supply voltage of the device drops to within a range of 0.9V~V such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the RSTFC register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~ V must exist for a time greater than that specified by t in the LVD/LVR characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual V value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the LVR will reset the device after 2~3 f LIRC clock cycles. When this happens, the LRF bit in the RSTFC register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. RSTD Inte�nal Reset Note: t is power-on delay with typical time=50 ms RSTD Low Voltage Reset Timing Chart •...
  • Page 97 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • RSTFC Register Name — — — — RSTF LVRF — — — — — — — — “x”: unknown Bit 7~4 Unimplemented, read as “0” Bit 3 RSTF: Reset control register software reset flag Described elsewhere. Bit 2 LVRF: LVR function reset flag 0: Not occurred 1: Occurred This bit is set to 1 when a specific low voltage reset condition occurs. Note that this bit can only be cleared to 0 by the application program.

  • Page 98: Reset Initial Conditions

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: Reset Function Powe�-on �eset LVR reset during NORMAL or SLOW Mode operation WDT time-out reset during NORMAL or SLOW Mode operation WDT ti�e-out �eset du�ing IDLE o�...
  • Page 99 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LVR Reset WDT Time-out WDT Time-out Reset Register (Normal (Normal (IDLE or (Power On) Operation) Operation) SLEEP)* IAR0 ● ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
  • Page 100 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LVR Reset WDT Time-out WDT Time-out Reset Register (Normal (Normal (IDLE or (Power On) Operation) Operation) SLEEP)* ● - 1 1 1 - - - - - 1 1 1 - - - -...
  • Page 101 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LVR Reset WDT Time-out WDT Time-out Reset Register (Normal (Normal (IDLE or (Power On) Operation) Operation) SLEEP)* FC� ● ● ● - - - - - - - 0 - - - - - - - 0...
  • Page 102 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LVR Reset WDT Time-out WDT Time-out Reset Register (Normal (Normal (IDLE or (Power On) Operation) Operation) SLEEP)* TKTMR ● ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
  • Page 103 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LVR Reset WDT Time-out WDT Time-out Reset Register (Normal (Normal (IDLE or (Power On) Operation) Operation) SLEEP)* TKM�C1 ● ● 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0...

  • Page 104: Input/Output Ports

    PE� PEC7 PEC� PEC� PEC4 PEC3 PEC� PEC1 PEC0 PEPU PEPU7 PEPU� PEPU� PEPU4 PEPU3 PEPU� PEPU1 PEPU0 I/O Registers List – BS67F340 Register Name PA� PA� PA� PAC7 PAC� PAC� PAC4 PAC3 PAC� PAC1 PAC0 PAPU PAPU7 PAPU� PAPU�...
  • Page 105 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Register Name PA� PA� PA� PAC7 PAC� PAC� PAC4 PAC3 PAC� PAC1 PAC0 PAPU PAPU7 PAPU� PAPU� PAPU4 PAPU3 PAPU� PAPU1 PAPU0 PAWU PAWU7 PAWU� PAWU� PAWU4 PAWU3 PAWU� PAWU1 PAWU0 PB�...
  • Page 106 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Register Name PA� PA� PA� PAC7 PAC� PAC� PAC4 PAC3 PAC� PAC1 PAC0 PAPU PAPU7 PAPU� PAPU� PAPU4 PAPU3 PAPU� PAPU1 PAPU0 PAWU PAWU7 PAWU� PAWU� PAWU4 PAWU3 PAWU� PAWU1 PAWU0 PB�...

  • Page 107: Pull-High Resisto�S

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using the relevant pull-high control registers and are implemented using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as an input or NMOS output. Otherwise, the pull-high resistors can not be enabled. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. Note that the wake-up function can be controlled by the wake-up control registers only when the pin-shared functional pin is selected as general purpose input/output and the MCU enters the Power down mode. I/O Port Control Registers Each Port has its own control register, known as PAC~PHC, which controls the input/output configuration. With this control register, each I/O pin with or without pull-high resistors can be...

  • Page 108: Pin-Sha�Ed Fun�Tions

    PDS11 PDS10 PES0 PES07 PES0� PES0� PES04 PES03 PES0� PES01 PES00 PES1 PES17 PES1� PES1� PES14 PES13 PES1� PES11 PES10 — — IFS� IFS4 IFS3 IFS� IFS1 IFS0 Pin-shared Function Selection Registers List – BS67F340 Rev. 1.40 De�e��e� 1�� �01�...
  • Page 109 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Register Name PAS0 PAS07 PAS0� PAS0� PAS04 PAS03 PAS0� PAS01 PAS00 PAS1 PAS17 PAS1� PAS1� PAS14 PAS13 PAS1� PAS11 PAS10 PBS0 PBS07 PBS0� PBS0� PBS04 PBS03 PBS0� PBS01 PBS00 PBS1 PBS17 PBS1�...
  • Page 110 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PAS0 Register Name PAS07 PAS0� PAS0� PAS04 PAS03 PAS0� PAS01 PAS00 Bit 7~6 PAS07~PAS06: PA3 pin function selection 00/11: PA3 01: SCS 10: XT1 Bit 5~4 PAS05~PAS04: PA2 pin function selection 00/10/11: PA2 01: SCS Bit 3~2 PAS03~PAS02: PA1 pin function selection 00/10: PA1 01: CTP0 11: V2 PAS01~PAS00: PA0 pin function selection Bit 1~0 00/10/11: PA0 01: SDO • PAS1 Register...
  • Page 111 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PBS0 Register Name PBS07 PBS0� PBS0� PBS04 PBS03 PBS0� PBS01 PBS00 Bit 7~6 PBS07~PBS06: PB3 pin function selection 00/10: PB3/INT0 01: RX 11: AN3 Bit 5~4 PBS05~PBS04: PB2 pin function selection 00: PB2/PTPI 01: TX 10: PTP 11: AN2 Bit 3~2 PBS03~PBS02: PB1 pin function selection 00/10: PB1 01: SCK/SCL 11: AN1 PBS01~PBS00: PB0 pin function selection Bit 1~0 00: PB0...
  • Page 112 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PCS0 Register Name PCS07 PCS0� PCS0� PCS04 PCS03 PCS0� PCS01 PCS00 Bit 7~6 PCS07~PCS06: PC3 pin function selection PCS0[7:6] BS67F340 BS67F350 BS67F360 BS67F370 KEY8 KEY8 KEY8 KEY8 SEG3 SEG3 SEG3 PCS05~PCS04: PC2 pin function selection Bit 5~4 PCS0[5:4] BS67F340 BS67F350...
  • Page 113 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PCS1 Register Name PCS17 PCS1� PCS1� PCS14 PCS13 PCS1� PCS11 PCS10 Bit 7~6 PCS17~PCS16: PC7 pin function selection PCS1[7:6] BS67F340 BS67F350 BS67F360 BS67F370 — — — KEY12 KEY12 KEY12 — SEG7 SEG7 PCS15~PCS14: PC6 pin function selection Bit 5~4 PCS1[5:4]...
  • Page 114 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PDS0 Register Name PDS07 PDS0� PDS0� PDS04 PDS03 PDS0� PDS01 PDS00 Bit 7~6 PDS07~PDS06: PD3 pin function selection PDS0[7:6] BS67F340 BS67F350 BS67F360 BS67F370 — — — KEY16 KEY16 KEY16 — SEG3 SEG11 SEG11 PDS05~PDS04: PD2 pin function selection Bit 5~4...
  • Page 115 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PDS1 Register Name — — PDS1� PDS14 PDS13 PDS1� PDS11 PDS10 — — — — Bit 7~6 “—” Unimplemented, read as 0 Bit 5~4 PDS15~PDS14: PD6 pin function selection PDS1[5:4] BS67F340 BS67F350 BS67F360 BS67F370 PD� PD� PD� PD� PD� PD�...
  • Page 116 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PES0 Register Name PES07 PES0� PES0� PES04 PES03 PES0� PES01 PES00 Bit 7~6 PES07~PES06: PE3 pin function selection PES0[7:6] BS67F340 BS67F350 BS67F360 BS67F370 PE3/STPI PE3/STPI PE3/STPI PE3/STPI STPB STPB STPB STPB PE3/STPI PE3/STPI KEY24 KEY24 SEG1�...
  • Page 117 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PES1 Register Name PES17 PES1� PES1� PES14 PES13 PES1� PES11 PES10 Bit 7~6 PES17~PES16: PE7 pin function selection PES1[7:6] BS67F340 BS67F350 BS67F360 BS67F370 CTP1B CTP1B CTP1B CTP1B KEY16 KEY28 KEY28 SEG11 SEG1� SEG�3 SEG�3 PES15~PES14: PE6 pin function selection...
  • Page 118 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PFS0 Register – BS67F360/BS67F370 Name PFS07 PFS0� PFS0� PFS04 PFS03 PFS0� PFS01 PFS00 Bit 7~6 PFS07~PFS06: PF3 pin function selection 00/01/10: PF3 11: SEG31 Bit 5~4 PFS05~PFS04: PF2 pin function selection 00/01/10: PF2 11: SEG30 Bit 3~2 PFS03~PFS02: PF1 pin function selection 00/01: PF1 10: OSC2 11: SEG29 Bit 1~0 PFS01~PFS00: PF0 pin function selection 00/01: PF0 10: OSC1 11: SEG28 •...
  • Page 119 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PGS1 Register – BS67F370 Name PGS17 PGS1� PGS1� PGS14 PGS13 PGS1� PGS11 PGS10 Bit 7~6 PGS17~PGS16: PG7 pin function selection 00/01/11: PG7 10: KEY36 Bit 5~4 PGS15~PGS14: PG6 pin function selection 00/01/11: PG6 10: KEY35 Bit 3~2 PGS13~PGS12: PG5 pin function selection 00/01/11: PG5 10: KEY34 Bit 1~0 PGS11~PGS10: PG4 pin function selection 00/01/11: PG4 10: KEY33 • PHS0 Register – BS67F370...
  • Page 120 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • PHS1 Register – BS67F370 Name PHS17 PHS16 PHS15 PHS14 PHS13 PHS12 PHS11 PHS10 Bit 7~6 PHS17~PHS16: PH7 pin function selection 00/01/10: PH7 11: SEG47 Bit 5~4 PHS15~PHS14: PH6 pin function selection 00/01/10: PH6 11: SEG46 Bit 3~2 PHS13~PHS12: PH5 pin function selection 00/01/10: PH5 11: SEG45 Bit 1~0 PHS11~PHS10: PH4 pin function selection 00/01/10: PH4 11: SEG44 • IFS Register Name —...

  • Page 121: I/O Pin Structures

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. P u l l - H i g h R e g i s t e r C o n t r o l B i t...

  • Page 122: Timer Modules - Tm

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Programming Considerations Within the user program, one of the things first to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set to high. This means that all I/O pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two...

  • Page 123: Tm Ope�Ation

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver TM Operation The different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. When the free running count-up counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTMn control registers, where “x” stands for C, S or P type TM and “n” stands for the specific TM serial number. For STM and PTM there is no serial number “n” in the relevant pin or control bits since there is only one STM and PTM respectively in the series of devices, The clock source can be a ratio of the system clock, f , or the internal high clock, f , the f clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source for event counting. TM Interrupts The Compact, Standard or Periodic type TM has two internal interrupt, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one or two TM input pins, with the label xTCKn and xTPnI respectively. The xTMn input pin, xTCKn, is essentially a clock source for the xTMn and is...

  • Page 124: Tm Input/Output Pin Selection

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Device Input Output Input Output Input Output BS�7F340 BS�7F3�0 CTCK0 CTP0� CTP0B STCK� STPI STP� STPB PTCK� PTPI PTP� PTPB BS�7F3�0 CTCK1 CTP1� CTP1B BS�7F370 TM External Pins TM Input/Output Pin Selection...
  • Page 125 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the “MOV” instruction to access the CCRA and CCRP low byte registers, named xTMnAL and PTMRPL, using the following access procedures. Accessing the CCRA or CCRP low byte registers without following these access procedures will result in unpredictable values. xTMn Counte� Registe� (Read only) xTMnDL xTMnDH 8-�it Buffe� xTMnAL xTMnAH xTMn CCRA Register (Read/Write)
  • Page 126 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Compact Type TM – CTM Although the simplest form of the TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pin. Device CTM Core CTM Input Pin CTM Output Pin Note BS�7F340 BS�7F3�0 10-�it CTM CTP0� CTP0B CTCK0� CTCK1 n=0 ~ 1 BS�7F3�0 (CTM0� CTM1) CTP1�...
  • Page 127 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Compact Type TM Register Description Overall operation of the Compact TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes and as well as the three CCRP bits. Register Name CTMnC0 CTnPAU CTnCK� CTnCK1 CTnCK0 CTnON CTnRP� CTnRP1 CTnRP0 CTMnC1 CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR CTMnDL D�...
  • Page 128 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver CTMnAH Register Name — — — — — — — — — — — — — — — — — — Bit 7~2 Unimplemented, read as “0” Bit 1~0 CTMn CCRA High Byte Register bit 1 ~ bit 0 CTMn 10-bit CCRA bit 9 ~ bit 8 CTMnC0 Register Name CTnPAU CTnCK�...
  • Page 129 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver CTnRP2~CTnRP0: CTMn CCRP 3-bit register, compared with the CTMn Counter Bit 2~0 bit 9 ~ bit 7 000: 1024 CTMn clocks 001: 128 CTMn clocks 010: 256 CTMn clocks 011: 384 CTMn clocks 100: 512 CTMn clocks 101: 640 CTMn clocks 110: 768 CTMn clocks 111: 896 CTMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the CTnCCLR bit is set to zero. Setting the CTnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
  • Page 130 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver In the Compare Match Output Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output pin changes state when a compare match occurs from the Comparator A. The CTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the CTMn output pin should be setup using the CTnOC bit in the CTMnC1 register. Note that the output level requested by the CTnIO1 and CTnIO0 bits must be different from the initial value setup using the CTnOC bit otherwise no change will occur on the CTMn output pin when a compare match occurs. After the CTMn output pin changes state, it can be reset to its initial level by changing the level of the CTnON bit from low to high. In the PWM Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the CTnIO1 and CTnIO0 bits only after the CTMn has been switched off. Unpredictable PWM outputs will occur if the CTnIO1 and CTnIO0 bits are changed when the CTMn is running. Bit 3 CTnOC: CTPn Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode 0: Active low 1: Active high This is the output control bit for the CTMn output pin. Its operation depends upon whether CTMn is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the CTMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the CTMn output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low.
  • Page 131 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Compact Type TM Operation Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the CTnM1 and CTnM0 bits in the CTMnC1 register. Compare Match Output Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register, should be set to “00” respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match...
  • Page 132 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value Counte� ove�flow CTnCCLR = 0; CTnM [1:0] = 00 CCRP > 0 CCRP=0 Counte� �lea�ed �y CCRP value 0x3FF CCRP > 0 Counte� Resu�e Resta�t CCRP Pause Stop CCRA Ti�e...
  • Page 133 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value CTnCCLR = 1; CTnM [1:0] = 00 CCRA = 0 CCRA > 0 Counte� �lea�ed �y CCRA value Counte� ove�flow 0x3FF CCRA=0 Resu�e CCRA Pause Stop Counte� Resta�t CCRP Ti�e...
  • Page 134 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Timer/Counter Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the CTMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the CTMn output pin is not...
  • Page 135 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value CTnDPX = 0; CTnM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when CTnON returns high CCRP Counte� Stop if Pause Resu�e CTnON bit low CCRA Ti�e CTnON...
  • Page 136 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value CTnDPX = 1; CTnM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when CTnON returns high CCRA Counte� Stop if Pause Resu�e CTnON bit low CCRP Ti�e CTnON...

  • Page 137: Standard Type Tm - Stm

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with two external input pins and can drive two external output pin. Device STM Core STM Input Pin STM Output Pin BS�7F340 BS�7F3�0 1�-�it STM STCK� STPI STP� STPB BS�7F3�0 BS�7F370 CCRP Co�pa�ato� P Mat�h 8-�it Co�pa�ato�...
  • Page 138 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The STMRP register is used to store the 8-bit CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name STMC0 STPAU STCK� STCK1 STCK0 STON — — — STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR STMDL D�...
  • Page 139 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver STMC0 Register Name STPAU STCK� STCK1 STCK0 STON — — — — — — — — — Bit 7 STPAU: STM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the STM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 STCK2~STCK0: Select STM Counter clock 000: f 001: f 010: f...
  • Page 140 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver STMC1 Register Name STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR Bit 7~6 STM1~STM0: Select STM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the STM. To ensure reliable operation the STM should be switched off before any changes are made to the STM1 and STM0 bits. In the Timer/Counter Mode, the STM output pin control will be disabled. Bit 5~4 STIO1~STIO0: Select STM external pin (STP or STPI) function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output...
  • Page 141 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver STOC: STM STP Output control Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the STM output pin. Its operation depends upon whether STM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the STM is in the Timer/Counter...

  • Page 142: Standa�D Type Tm Ope�Ation Modes

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver STMRP Register Name STRP7 STRP� STRP� STRP4 STRP3 STRP� STRP1 STRP0 Bit 7~0 STRP7~STRP0: STM CCRP 8-bit register, compared with the STM counter bit15~bit8 Comparator P match period = 0: 65536 STM clocks 1~255: (1~255) × 256 STM clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the STCCLR bit is set to zero. Setting the STCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples.
  • Page 143 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� ove�flow Counte� Value STCCLR = 0; STM [1:0] = 00 CCRP > 0 CCRP=0 Counte� �lea�ed �y CCRP value 0xFFFF CCRP > 0 Counte� Resu�e Resta�t CCRP Pause Stop CCRA Ti�e...
  • Page 144 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value STCCLR = 1; STM [1:0] = 00 CCRA = 0 CCRA > 0 Counte� �lea�ed �y CCRA value Counte� ove�flow 0xFFFF CCRA=0 Resu�e CCRA Pause Stop Counte� Resta�t CCRP Ti�e...
  • Page 145 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the STM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within the STM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values.
  • Page 146 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value STDPX = 0; STM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when STON returns high CCRP Counte� Stop if Pause Resu�e STON bit low CCRA Ti�e STON...
  • Page 147 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value STDPX = 1; STM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when STON returns high CCRA Counte� Stop if Pause Resu�e STON bit low CCRP Ti�e STON...
  • Page 148 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Single Pulse Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin. The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can be implemented using the application program. However in the Single Pulse Mode, the STON bit can also be made to automatically change from low to high using the external STCK pin, which will in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The STON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter can only be reset back to zero when the STON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in this Mode. CCRA CCRA Leading Edge T�ailing Edge S/W Co��and S/W Co��and SET“STON”...
  • Page 149 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value STM [1:0] = 10 ; STIO [1:0] = 11 Counte� stopped �y CCRA Counte� Reset when STON returns high CCRA Counte� Stops Resu�e Pause �y softwa�e CCRP Ti�e STON Auto.
  • Page 150 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STPI pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in the STMC1 register. The counter is started when the STON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STPI pin the present value in the counter will be latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on the STPI pin the counter will continue to free run until the STON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a STM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1 and STIO0 bits can select the active trigger edge on the STPI pin to be a rising edge, falling edge or both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STPI pin, however it must be noted that the counter will continue to run. The STCCLR and STDPX bits are not used in this Mode. Rev. 1.40 1�0 De�e��e� 1�� �01�...
  • Page 151 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value STM [1:0] = 01 Counte� �lea�ed �y CCRP Counte� Counte� Stop Reset CCRP Resu�e Pause Ti�e STON STPAU A�tive A�tive A�tive edge edge edge STM �aptu�e pin STPI CCRA Int.

  • Page 152: Periodic Type Tm - Ptm

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with two external input pins and can drive two external output pin. Device PTM Core PTM Input Pin PTM Output Pin BS�7F340 BS�7F3�0 10-�it PTM PTCK� PTPI PTP� PTPB BS�7F3�0 BS�7F370 CCRP Co�pa�ato� P Mat�h 10-�it Co�pa�ato�...
  • Page 153 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name PTMC0 PTPAU PTCK� PTCK1 PTCK0 PTON — — — PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR PTMDL D�...
  • Page 154 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver PTMAH Register Name — — — — — — — — — — — — — — — — — — Bit 7~2 Unimplemented, read as “0” Bit 1~0 PTM CCRA High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRA bit 9 ~ bit 8 PTMRPL Register Name PTRP7 PTRP�...
  • Page 155 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver PTCK2~PTCK0: Select PTM Counter clock Bit 6~4 000: f 001: f 010: f 011: f 100: f 101: f 110: PTCK rising edge clock 111: PTCK falling edge clock These three bits are used to select the clock source for the PTM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source f is the system clock, while f and f are other internal clocks, the details of which can be found in the oscillator section. Bit 3 PTON: PTM Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the PTM. Setting the bit high enables the counter to run while clearing the bit disables the PTM. Clearing this bit to zero will stop the counter from counting and turn off the PTM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTM is in the Compare Match Output Mode then the PTM output pin will be reset to its initial condition, as specified by the PTOC bit, when the PTON bit changes from low to high. Bit 2~0 Unimplemented, read as “0”...
  • Page 156 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Capture Input Mode 00: Input capture at rising edge of PTPI or PTCK 01: Input capture at falling edge of PTPI or PTCK 10: Input capture at rising/falling edge of PTPI or PTCK 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTM is running. In the Compare Match Output Mode, the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a compare match occurs from the Comparator A. The PTM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTM output pin should be setup using the PTOC bit in the PTMC1 register. Note that the output level requested by the PTIO1 and PTIO0 bits must be different from the initial value setup using the PTOC bit otherwise no change will occur on the PTM output pin when a compare match occurs. After the PTM output pin changes state, it can be reset to its initial level by changing the level of the PTON bit from low to high. In the PWM Mode, the PTIO1 and PTIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PTM output function...
  • Page 157 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver PTCCLR: PTM Counter Clear condition selection Bit 0 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. Periodic Type TM Operation Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register. Compare Match Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMAF and PTMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated.
  • Page 158 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� ove�flow Counte� Value PTCCLR = 0; PTM [1:0] = 00 CCRP > 0 CCRP=0 Counte� �lea�ed �y CCRP value 0x3FF CCRP > 0 Counte� Resu�e Resta�t CCRP Pause Stop CCRA Ti�e...
  • Page 159 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value PTCCLR = 1; PTM [1:0] = 00 CCRA = 0 CCRA > 0 Counte� �lea�ed �y CCRA value Counte� ove�flow 0x3FF CCRA=0 Resu�e CCRA Pause Stop Counte� Resta�t CCRP Ti�e...
  • Page 160 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Timer/Counter Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the PTM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 10 respectively. The PWM function within the PTM is useful for applications which require functions such as motor control, heating control, illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the PTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values.
  • Page 161 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value PTM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when PTON returns high CCRP Counte� Stop if Pause Resu�e PTON bit low CCRA Ti�e PTON PTPAU PTPOL CCRA Int.
  • Page 162 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Single Pulse Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin. The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTON bit can also be made to automatically change from low to high using the external PTCK pin, which will in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTM interrupt. The counter can only be reset back to zero when the PTON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTCCLR is not used in this Mode. CCRA CCRA Leading Edge T�ailing Edge S/W Co��and S/W Co��and SET“PTON”...
  • Page 163 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value PTM [1:0] = 10 ; PTIO [1:0] = 11 Counte� stopped �y CCRA Counte� Reset when PTON returns high CCRA Counte� Stops Resu�e Pause �y softwa�e CCRP Ti�e PTON Auto.
  • Page 164 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Capture Input Mode To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPI or PTCK pin, selected by the PTCAPTS bit in the PTMC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register. The counter is started when the PTON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPI or PTCK pin the present value in the counter will be latched into the CCRA registers and a PTM interrupt generated. Irrespective of what events occur on the PTPI or PTCK pin the counter will continue to free run until the PTON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI or PTCK pin to be a rising edge, falling edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPI or PTCK pin, however it must be noted that the counter will continue to run. As the PTPI or PTCK pin is pin shared with other functions, care must be taken if the PTM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTCCLR, PTOC and PTPOL bits are not used in this Mode. Rev. 1.40 1�4 De�e��e� 1�� �01�...
  • Page 165 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Counte� Value PTM [1:0] = 01 Counte� �lea�ed �y CCRP Counte� Counte� Stop Reset CCRP Resu�e Pause Ti�e PTON PTPAU A�tive A�tive A�tive edge edge edge PTM �aptu�e pin PTPI o� PTCK CCRA Int.

  • Page 166: Analog To Digital Converter

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview These devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. It also can convert the internal signals, such as the Temperature semsor output or Temperature sensor reference voltage, into a 12-bit digital value. The external or internal analog signal to be converted is determined by the ACS3~ACS0 bits together with the TSE and BGMEN bits. When the external analog signal is to be converted, the corresponding pin-shared...
  • Page 167 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver ÷ � ADCK�~ADCK0 Pin-sha�ed (N=0~7) ADCEN Sele�tion ACS3~ACS0 TSCLK_S1~TSCLK_S0 A/D Clo�k ADRL A/D Data A/D Conve�te� Registe�s ADRH 1xxxB ADRFS TSVREF START ADBZ IDLE_CONV A/D Conve�te� Refe�en�e Voltage BGMEN OP�EN PTAT OPA�...
  • Page 168 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver A/D Converter Data Registers – ADRL, ADRH As these devices contain an internal 12-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. Note that the A/D data register contents can only be read in the A/ D conversion completion interrupt service subroutine when the Auto-conversion mode is enabled by setting the ATM bit in the ADCR1 register to 1. The A/D data registers contents will be cleared to zero if the A/D converter is disabled. ADRH...
  • Page 169 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • ADCR0 Register Name START ADBZ ADCEN ADRFS ACS3 ACS� ACS1 ACS0 Bit 7 START: Start the A/D Conversion 0→1→0: Start This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. ADBZ: A/D Converter busy flag Bit 6 0: No A/D conversion is in progress 1: A/D conversion is in progress This read only flag is used to indicate whether the A/D conversion is in progress or not. When the START bit is set from low to high and then to low again, the ADBZ flag will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be cleared to 0 after the A/D conversion is complete. ADCEN: A/D Converter function enable control Bit 5 0: Disable 1: Enable This bit controls the A/D internal function. This bit should be set to one to enable the A/D converter. If the bit is set low, then the A/D converter will be switched off reducing the device power consumption. When the A/D converter function is disabled,...
  • Page 170 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • ADCR1 Register Name — IDLE_CONV VREFS — ADCK� ADCK1 ADCK0 — — — — Bit 7 ATM: A/D auto-conversion mode enable control 0: Disable 1: Enable When this bit is set to 1, the A/D converter will continuously perform the data conversion after the current conversion is complete without configuring the “START”...
  • Page 171 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • TSC0 Register Name BGMEN G5XEN K_REFO — — — — — — — — — — — — — — — Bit 7 BGMEN: Temperature sensor reference voltage output function enable control 0: Disable 1: Enable This bit controls the internal temperature sensor reference voltage output function and is only available when the TSE bit is set to 1. The internal temperature sensor reference voltage can be converted when the TSE and BGMEN bits are set to 1 and the ACS bit field is set to “1xxx”. However, the internal temperature sensor output voltage will be converted if the TSE bit is set to 1 and the BGMEN bit is cleared to 0 together with ACS bit field equal to “1xxx”.
  • Page 172 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • TSC2 Register Name VREFP_EXT BIAS D� D� TSCLK_S1 TSCLK_S0 Bit 7 VREFP_EXT: A/D converter positive reference voltage select 0: Temperature reference voltage – V TSVREF 1: Determined by VREFS bit This bit is used to select the A/D converter positive reference voltage. When this bit is set to 1, the A/D converter reference voltage is determines by the VREFS bit in the ADCR1 register. However, this bit should be set low to select the V voltage as TSVREF the A/D converter reference voltage together with proper configurations of the OPA2 input signal and gain. Bit 6 BIAS: OPA2 bias voltage select 0: V TSVREF 1: Internal A/D converter power Bit 5~2 D5~D2: Data bits for internal used These bits should be kept low and can not be changed. Bit 1~0...

  • Page 173: A/D Operation

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver A/D Operation The START bit in the ADCR0 register is used to start the AD conversion. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. The ADBZ bit in the ADCR0 register is used to indicate whether the analog to digital conversion process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ will be cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can poll the ADBZ bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock f , can be chosen to be either f or a subdivided version of f . The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Although the A/D clock source is determined by the...

  • Page 174: A/D Reference Voltage

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver A/D Reference Voltage The reference voltage supply to the A/D Converter can be supplied from the positive power supply pin, V , an external reference source supplied on pin VREF or an internal temperature sensor reference voltage V . The internal temperature sensor reference voltage can be derived from the TSVREF intenal V or V voltage selected using the K_VPTAT bit in the TSC3 register and then amplified PTAT through a programmable gain amplifier except the one sourced from V . The PGA gain can be equal to 1.675 or 1 selected by the K_REFO bit in the TSC0 register. As the VREF pin is pin-shared with other functions, when the VREF pin is selected as the reference voltage supply pin, the VREF pin-shared function control bits should first be properly configured to disable other pin-shared functions. A/D Input Pins All of the external A/D analog input pins are pin-shared with the I/O pins as well as other functions.

  • Page 175: Summary Of A/D Conversion Steps

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver ON�ST ADCEN A/D sa�pling ti�e A/D sa�pling ti�e START Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion ADBZ End of A/D End of A/D �onve�sion �onve�sion ACS[3:0]...

  • Page 176: A/D Transfer Function

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADCEN low in the ADCR register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the reference voltage, this gives a single bit analog input value of reference voltage value divided by 4096. 1 LSB=V ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage=A/D output digital value × V ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the V level. 1 . 5 L S B F F F H...

  • Page 177: A/D Programming Examples

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver A/D Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an ADBZ polling method to detect the end of conversion clr ADE ;...
  • Page 178 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt set VREFP_EXT ; deselect the temperature sensor reference voltage mov a,03H ; select f...

  • Page 179: Serial Interface Module - Sim

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four-line SPI interface or two-line I C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM interface functional pins must first be selected using the corresponding pin-shared function selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pull- high control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices.
  • Page 180 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver S P I M a s t e r S P I S l a v e S C K S C K S D O S D I S D I...
  • Page 181 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I C function. The SIMC1 register is not used by the SPI function, only by the I C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag, etc. • SIMC0 Register Name SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF — — SIM2~SIM0: SIM Operating Mode Control Bit 7~5 000: SPI master mode; SPI clock is f 001: SPI master mode; SPI clock is f /16 010: SPI master mode; SPI clock is f /64 011: SPI master mode; SPI clock is f 100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2 101: SPI slave mode...
  • Page 182 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • SIMC2 Register Name D� CKPOLB CKEG CSEN WCOL Bit 7~6 Undefined bits These bits can be read or written by the application program. CKPOLB: SPI clock line base condition selection Bit 5 0: The SCK line will be high when the clock is inactive. 1: The SCK line will be low when the clock is inactive. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: SPI SCK clock active edge type selection CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK...
  • Page 183 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output a SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. S I M E N = 1 , C S E N = 0 ( E x t e r n a l P u l l - H i g h )
  • Page 184 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver S C S S C K ( C K P O L B = 1 ) S C K ( C K P O L B = 0 ) S D O...
  • Page 185 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver C Interface The I C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. V D D S D A S C L D e v i c e...
  • Page 186 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver S T A R T s i g n a l f r o m M a s t e r S e n d s l a v e a d d r e s s...
  • Page 187 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I C functions. Before the device writes data to the I C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I C bus must be made via the SIMD register. Name D� D� D� “x”: unknown • SIMA Register The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Name IICA� IICA�...
  • Page 188 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • SIMC0 Register Name SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF — — Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is f 001: SPI master mode; SPI clock is f /16 010: SPI master mode; SPI clock is f /64 011: SPI master mode; SPI clock is f 100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2 101: SPI slave mode 110: I C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from TM0. If the SPI Slave Mode is selected then the...
  • Page 189 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver • SIMC1 Register Name HAAS TXAK IAMWU RXAK Bit 7 HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.
  • Page 190 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver RXAK: I Bit 0 C bus receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is “0”, it means that a acknowledge signal has been received at the 9 clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is “1”. When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I C Bus. C Bus Communication Communication on the I C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS and SIMTOF bits to determine whether the interrupt source originates from an address match, 8-bit data transfer completion or C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8 bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or...
  • Page 191 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver S t a r t S E T S I M [ 2 : 0 ] = 1 1 0 S E T S I M E N W r i t e S l a v e...
  • Page 192 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no...
  • Page 193 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver S t a r t Y e s S I M T O F = 1 S E T S I M T O E N Y e s H A A S = 1...
  • Page 194 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver S t a r t S l a v e A d d r e s s S R W A C K S C L S D A I C t i m e - o u t...

  • Page 195: Uart Interface

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver UART Interface These devices contain an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, asynchronous communication • 8 or 9 bits character length...
  • Page 196 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver UART External Pin To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. The TX and RX pin function should first be selected by the corresponding pin-shared function selection register before the UART function is used. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O or other pin-shared functional pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX and RX pins. When the TX or RX pin function is disabled by clearing the UARTEN, TXEN or RXEN bit, the TX or RX pin will be set to a floating state. At this time whether the internal pull- high resistor is connected to the TX or RX pin or not is determined by the corresponding I/O pull- high function control bit. UART Data Transfer Scheme The above diagram shows the overall data transfer structure arrangement for the UART interface. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the TXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR_RXR register is used...
  • Page 197 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver USR Register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only and further explanations are given below. Name PERR FERR OERR RIDLE RXIF TIDLE TXIF PERR: Parity error flag...
  • Page 198 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver RIDLE: Receiver status Bit 3 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is “0”, it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is “1”, it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is “1” indicating that the UART receiver is idle and the RX pin stays in logic high condition. Bit 2 RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is “0”, it indicates that the RXR read data register is empty. When the flag is “1”, it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1 TIDLE: Transmission status 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is “0”, it indicates that a transmission is in progress. This flag will be set to “1” when the TXIF flag is “1” and when there is no transmit data or break character being transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state...
  • Page 199 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver UCR1 Register The UCR1 register together with the UCR2 register are the UART control registers that are used to set the various options for the UART function such as overall on/off control, parity control, data transfer bit length, etc. Further explanation on each of the bits is given below. Name UARTEN PREN STOPS TXBRK “x”: unknown Bit 7 UARTEN: UART function enable control 0: Disable UART; TX and RX pins are in a floating state. 1: Enable UART; TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to “0”, the UART will be disabled and the RX pin as well as the TX pin will be set in a floating state. When the bit is equal to “1”, the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6 BNO: Number of data transfer bits selection 0: 8-bit data transfer...
  • Page 200 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver TXBRK: Transmit break character Bit 2 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is equal to “0”, there are no break characters and the TX pin operats normally. When the bit is equal to “1”, there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to “1”, after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1 RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. Bit 0 TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. UCR2 Register The UCR2 register is the second of the UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation if the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable.
  • Page 201 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver BRGH: Baud Rate speed selection Bit 5 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register, BRG, controls the baud rate of the UART. If the bit is equal to 0, the low speed mode is selected. Bit 4 ADDEN: Address detect function enable control 0: Address detection function is disabled 1: Address detection function is enabled The bit named ADDEN is the address detection function enable control bit. When this bit is equal to 1, the address detection function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, has a value of “1”, then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of the BNO bit. If the address bit known as the 8th or 9th bit of the received word is “0” with the address detection function being enabled, an interrupt will not be generated and the received data will be discarded. WAKE: RX pin falling edge wake-up function enable control Bit 3 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled The bit enables or disables the receiver wake-up function. If this bit is equal to 1 and the device is in IDLE0 or SLEEP mode, a falling edge on the RX pin will wake up the device. If this bit is equal to 0 and the device is in IDLE or SLEEP mode, any edge transitions on the RX pin will not wake up the device. RIE: Receiver interrupt enable control Bit 2 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled The bit enables or disables the receiver interrupt. If this bit is equal to 1 and when the...
  • Page 202 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the BRG register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register, N, which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit Baud Rate (BR) [64(N+1)] [16(N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. BRG Register Name BRG7 BRG� BRG� BRG4 BRG3 BRG�...

  • Page 203: Uart Setup And Cont

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits and one or two stop bits. Parity is supported by the UART hardware and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the transmitter and receiver of the UART are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/Disabling the UART Interface The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and these two pins will be in a floating state. When the UART function is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the enable control, the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration.
  • Page 204 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver N e x t P a r i t y B i t S t a r t S t a r t B i t B i t 0 B i t 1...

  • Page 205: Uart Re�Eive

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Transmitting Break If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13xN “0” bits, where N=1, 2, etc. If a break character is to be transmitted, then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level, then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9 bit, which is the MSB, will be stored in the RX8 bit in the UCR1 register. At the receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the...
  • Page 206 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Receiving Data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin to the shift register, with the least significant bit LSB first. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while the 3 byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the byte has been completely shifted in, otherwise the 3 byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received, the following sequence of events will occur: • The RXIF bit in the USR register will be set when the RXR register has data available. There will be at most one more character available before an overrun error occurs. • When the contents of the shift register have been transferred to the RXR register and if the RIE bit is set, then an interrupt will be generated. • If during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access...
  • Page 207 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The read only receive interrupt flag, RXIF, in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a 3 byte can continue to be received. Before the 3 byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The OERR flag in the USR register will be set. • The RXR contents will not be lost.

  • Page 208: Uart Inte��Upt

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Parity Error – PERR The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity function is enabled, PREN=1, and if the parity type, odd or even, is selected. The read only PERR flag and the received data will be recorded in the USR and RXR registers respectively. It is cleared on any reset, it should be noted that the flags, FERR and PERR, in the USR register should first be read by the application program before reading the data word. UART Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these...

  • Page 209: Uart Powe� Down And Wake

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Address Detect Mode Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register, enables this special function. If this bit is set to 1, then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is equal to 1, then when the data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the microcontroller must also be enabled for correct interrupt generation. The highest address bit is the bit if the bit BNO=1 or the 8 bit if the bit BNO=0. If the highest bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is equal to 0, then a Receive Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detection and parity functions are mutually exclusive functions. Therefore, if the address detect function is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit PREN to zero. Bit 9 if BNO=1 ADDEN UART Interrupt Generated Bit 8 if BNO=0 √ √...

  • Page 210: Lcd Driver

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LCD Driver For large volume applications, which incorporate an LCD in their design, the use of a custom display rather than a more expensive character based display reduces costs significantly. However, the corresponding COM and SEG signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper LCD operation to occur. These devices all contain an LCD Driver function, which with their internal LCD signal generating circuitry and various options, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom LCDs. Device Duty Bias Bias Type Wave Type BS�7F340 BS�7F3�0 R o� C A o�...
  • Page 211 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver PLCD VA �ont�ol Qui�k �ha�ging �ont�ol LCDEN Note: When the R type LCD is disa�led� the DC path will �e swit�hed. COMn QT: Qui�k �ha�ging ti�e dete��ined �y QCT [�:0] R Type Bias Configuration – 1/3 Bias LCD Memory An area of Data Memory is especially reserved for use for the LCD display data. This data area...
  • Page 212 SEG �� SEG 30 SEG �3 SEG 31 24 SEG x 4 COM 32 SEG x 4 COM BS67F340 LCD Memory Map BS67F350 LCD Memory Map �3 �� �1 �0 �3 �� �1 �0 SEG 0 SEG 0 SEG 1 SEG 1 SEG �...

  • Page 213: Lcd Registe

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LCD Clock Source The LCD clock source is the internal clock signal, f , divided by 8 using an internal divider circuit. The f internal clock is supplied by either the LIRC or LXT oscillator, the choice of which is determined by a software control bit. For proper LCD operation, this arrangement is provided to generate an ideal LCD clock source frequency of 4 kHz. LCD Register There are control registers, named as LCDC0 and LCDC1, in the Data Memory which is used to control the various setup features of the LCD Driver. Various bits in this registers control functions such as LCD wave type, bias type, supply power selection, total bias resistor selection together with the overall LCD enable and disable control. The LCDEN bit in the LCDC0 register, which provides the overall LCD enable/disable function, will only be effective when the device is in the NOAMRL, SLOW or IDLE Mode. If the device is in the SLEEP Mode then the display will always be disabled. Bits, RSEL2 ~ RSEL0, in the LCDC0 register select the internal total bias resistors to supply the LCD panel with the proper bias current. A choice to best match the LCD panel used in the application can be selected also to minimise bias current. The TYPE bit in the LCDC0 register is used to select whether Type A or Type B LCD waveform signals are used. The RCT bit in the same register is used to select whether R Type or C Type LCD bias is used. The LCDP1 and LCDP0 bits are used to select that the LCD supply power comes from either the external pin or internal power supply for C type bias application.
  • Page 214 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LCDC0 Register Name TYPE LCDP1 LCDP0 RSEL� RSEL1 RSEL0 LCDEN Bit 7 TYPE: LCD waveform type selection 0: Type A 1: Type B Bit 6 RCT: LCD bias type selection 0: R type 1: C type Bit 5~4 LCDP1~LCDP0: C type bias LCD power supply selection 00: From external pin PLCD, V1 or V2 01: From internal reference voltage V supplied to VC REFIN 10: From internal voltage V supplied to VB 11: From internal voltage V supplied to VA The V is an internal reference voltage with an approximate level of 1.08V. REFIN...

  • Page 215: Lcd Voltage Sou

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LCDC1 Register Name QCT� QCT1 QCT0 — PLCD3 PLCD� PLCD1 PLCD0 — — Bit 7~5 QCT2~QCT0: R type quick charging time selection 000: 1 t 001: 2 t 010: 3 t 011: 4 t 100: 5 t 101: 6 t 110: 7 t 111: 8 t The t is the period of the LCD clock source f , i.e., 1/f Bit 4 Unimplemented, read as “0” Bit 3~0 PLCD3~PLCD0: R type bias supply voltage selection for VA 0000: 8/16 × PLCD 0001: 9/16 × PLCD...
  • Page 216 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver C Type Biasing For C type biasing the LCD voltage source can be supplied on the external pin PLCD, V1 or V2 or derived from the internal voltage source to generate the required biasing voltages. The C type bias voltage source is selected using the LCDP1 and LCDP0 bits in the LCDC0 register. The C type biasing scheme uses an internal charge pump circuit can generate voltages higher than what is supplied on PLCD or V2. This feature is useful in applications where the microcontroller supply voltage is less than the supply voltage required by the LCD. Additional charge pump capacitors must also be connected between pins C1 and C2 to generate the necessary voltage levels. For C type 1/3 bias external power supply scheme, the LCD power can be supplied on PLCD, V1 or V2 pin. However, the LCD power is internally supplied on VA, VB or VC for C type 1/3 bias internal power supply scheme. Four internally generated voltage levels V and V are utilised. These bias voltages have different levels depending upon different LCD power supply schemes. LCD Power Supply VA voltage VB voltage VC voltage on V1 2/3 × V 1/3 ×...
  • Page 217 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LCD Driver Output The number of COM and SEG outputs supplied by the LCD driver, as well as its biasing and wave type selections, are dependent upon how the LCD control bits are programmed. The Bias Type, whether C or R type is also selected by a software control bit. The nature of Liquid Crystal Displays require that only AC voltages can be applied to their pixels as the application of DC voltages to LCD pixels may cause permanent damage. For this reason the relative contrast of an LCD display is controlled by the actual RMS voltage applied to each pixel, which is equal to the RMS value of the voltage on the COM pin minus the voltage applied to the SEG pin. This differential RMS voltage must be greater than the LCD saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off. The requirement to limit the DC voltage to zero and to control as many pixels as possible with a minimum number of connections requires that both a time and amplitude signal is generated and applied to the application LCD. These time and amplitude varying signals are automatically generated by the LCD driver circuits in the microcontroller. What is known as the duty determines the number of common lines used, which are also known as backplanes or COMs. The duty, which is to have a value of 1/4 and which equates to a COM number of 4, therefore defines the number of time divisions within each LCD signal frame. Two types of signal generation are also provided, known as Type A and Type B, the required type is selected via the TYPE bit in the LCDC0 register. Type B offers lower frequency signals, however, lower frequencies may introduce flickering and influence display clarity. Rev. 1.40 �17 De�e��e� 1�� �01�...
  • Page 218 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LCD Display Off Mode COM0 ~ COM3 All seng�ent outputs 1 F�a�e Normal Operation Mode COM0 COM1 COM� COM3 All seg�ents a�e OFF COM0 side segments are ON COM1 side segments are ON...
  • Page 219 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LCD Display Off Mode COM0 ~ COM3 All seng�ent outputs 1 F�a�e Normal Operation Mode COM0 COM1 COM� COM3 All seg�ents a�e OFF COM0 side segments are ON COM1 side segments are ON...

  • Page 220: Touch Key Function

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Programming Considerations Certain precautions must be taken when programming the LCD. One of these is to ensure that the LCD Memory is properly initialised after the microcontroller is powered on. Like the General Purpose Data Memory, the contents of the LCD Memory are in an unknown condition after power-on. As the contents of the LCD Memory will be mapped into the actual display, it is important to initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. Consideration must also be given to the capacitive load of the actual LCD used in the application. As the load presented to the microcontroller by LCD pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the COM lines which may be connected to many LCD pixels. The accompanying diagram depicts the equivalent circuit of the LCD. One additional consideration that must be taken into account is what happens when the microcontroller enters the IDLE or SLOW Mode. The LCDEN control bit in the LCDC0 register...
  • Page 221 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Device Total Key Number Touch Key Module Touch Key KEY1~KEY4 KEY5~KEY8 M� KEY9~KEY12 KEY13~KEY16 BS�7F370 3� KEY17~KEY20 M� KEY21~KEY24 M� KEY25~KEY28 KEY29~KEY32 KEY33~KEY36 KEY1~KEY4 KEY5~KEY8 M� KEY9~KEY12 BS�7F3�0 �8 KEY13~KEY16 KEY17~KEY20 M�...
  • Page 222 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver KEY 1 TKMn16DH / TKMn16DL ( to Data Me�o�y Se�to� �) KEY 2 Mux . Multi- Filte� 16-bit C/F Counter TKCFOV f�equen�y KEY 3 MnDFEN KEY 4 TKMnC� TKMnROH / TKMnROL MnTSS ( f�o�...

  • Page 223: Touch Key Register Definition

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Touch Key Register Definition Each touch key module, which contains four touch key functions, has its own suite registers. The following table shows the register set for each touch key module. The Mn within the register name refers to the Touch Key module number. The series of devices has up to seven Touch Key Modules dependent upon the selected device. Name Description TKTMR Tou�h key ti�e slot 8-�it �ounte� p�oload �egiste� TKC0 Tou�h key fun�tion Cont�ol �egiste� 0 TKC1 Tou�h key fun�tion Cont�ol �egiste� 1 TK1�DL...
  • Page 224 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver TKTMR Register Name D� D� D� Bit 7~0 D7~D0: Touch key time slot 8-bit counter proload register The touch key time slot counter proload register is used to determine the touch key time slot overflow time. The time slot unit period is obtained by a 5-bit counter and equal to 32 time slot clock cycles. Therefore, the time slot counter overflow time is equal to the following equation shown. Time slot counter overflow time=(256 - TKTMR[7:0]) × 32t , where t is the time slot counter clock. TKC0 Register Name TKRAMC TKRCOV TKST TKCFOV TK1�OV — TKMOD TKBUSY — — Bit 7 TKRAMC: Touch key Data RAM access control...
  • Page 225 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver TKST: Touch key detection Start control Bit 5 0: Stopped or no operation 0→1: Start detection In all modules the touch key module 16-bit C/F counter, touch key function 16-bit counter and 5-bit time slot unit period counter will automatically be cleared when this bit is cleared to zero. However, the 8-bit programmable time slot counter will not be cleared. When this bit is changed from low to high, the touch key module 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unie period counter and 8-bit time slot counter will be switched on together with the key and reference oscillators to drive the corresponding counters. Bit 4 TKCFOV: Touch key module 16-bit C/F counter overflow flag 0: No overflow occurs 1: Overflow occurs This bit is set by touch key module 16-bit C/F counter overflow and must be cleared to 0 by application programs. Bit 3 TK16OV: Touch key function 16-bit counter overflow flag 0: No overflow occurs 1: Overflow occurs This bit is set by touch key function 16-bit counter overflow and must be cleared to 0 by application programs. Bit 2 Unimplemented, read as “0” Bit 1 TKMOD: Touch key scan mode select 0: Auto scan mode 1: Manual scan mode In manual scan mode the reference oscillator capacitor value should be properly configured before the scan operation begins and the touch key module 16-bit C/F counter value should be read after the scan operation finishes by application program.
  • Page 226 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver TKC1 Register Name D� D� TSCS TK1�S1 TK1�S0 TKFS1 TKFS0 Bit 7~5 D7~D5: Data bits for test only These bits are used for test purpose only and must be kept as “000” for normal operations. TSCS: Touch key time slot counter select Bit 4...
  • Page 227 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver TKMnROH/TKMnROL – Touch Key Module n Reference Oscillator Capacitor Select Register Pair Register TKMnROH TKMnROL Name — — — — — — D� D� D� — — — — — —...
  • Page 228 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver TKMnC1 Register Name MnTSS — MnROEN MnKOEN MnK4EN MnK3EN MnK2EN MnK1EN — — Bit 7 MnTSS: Touch key module n time slot counter clock source select 0: Touch key module n reference oscillator 1: f Bit 6 Unimplemented, read as “0” Bit 5 MnROEN: Touch key module n Reference oscillator enable control 0: Disable 1: Enable This bit is used to enable the touch key module n reference oscillator. In auto scan mode the reference oscillator will automatically be enabled by setting the MnROEN bit high when the TKST bit is set from low to high if the reference oscillator is selected as the time slot clock source. The combination of the MnTSS, TSCS and...
  • Page 229 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver TKMnC2 Register Name MnSK31 MnSK30 MnSK�1 MnSK�0 MnSK11 MnSK10 MnSK01 MnSK00 Bit 7~6 MnSK31~MnSK30: Touch key module n time slot 3 key scan select 00: KEY 1 01: KEY 2 10: KEY 3 11: KEY 4 These bits are used to select the desired scan key in time slot 3 and only available in the auto scan mode. MnSK21~MnSK20: Touch key module n time slot 2 key scan select Bit 5~4 00: KEY 1 01: KEY 2 10: KEY 3 11: KEY 4 These bits are used to select the desired scan key in time slot 2 and only available in the auto scan mode. MnSK11~MnSK10: Touch key module n time slot 1 key scan select Bit 3~2 00: KEY 1 01: KEY 2...

  • Page 230: Tou�H Key Inte��Upt

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Touch Key Operation When a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase. By using this capacitance variation to change slightly the frequency of the internal sense oscillator, touch actions can be sensed by measuring these frequency changes. Using an internal programmable divider the reference clock is used to generate a fixed time period. By counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined. TKST MnKOEN MnROEN Hardware set to “0”...
  • Page 231 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Each touch key module contains four touch key inputs which are shared logical I/O pins, and the desired function is selected using register bits. Each touch key has its own independent sense oscillator. There are therefore four sense oscillators within each touch key module. During this reference clock fixed interval, the number of clock cycles generated by the sense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. At the end of the fixed reference clock time interval a Touch Key interrupt signal will be...
  • Page 232 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Key Auto S�an Cy�le TKST Ti�e slot 0 Ti�e slot 1 Ti�e slot 1 Module 0 Ti�e slot � Ti�e slot � Ti�e slot 3 Ti�e slot 3 Ti�e slot 0 Ti�e slot 1...
  • Page 233 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver In the auto scan mode the key oscillator and reference oscillator will automatically be enabled when the TKST bit is set from low to high and disabled automatically when the TKBUSY bit changes from high to low. When the TKST bit is set from low to high in the auto scan mode, the first reference oscillator internal capacitor value will be read from a specific location of the dedicated touch key data memory and loaded into the corresponding TKMnROH/TKMnROL registers. Then the 16-bit C/F counter value will be written into the last location of the corresponding touch key module data memory. After this the selected key will be scanned in time slot 0. At the end of the time slot 0 key scan operation, the reference oscillator internal capacitor value for the next selected key will be read from the touch key data memory and loaded into the the next TKMnROH/TKMnROL registers. Then the 16-bit C/F counter value of the current scanned key will be written into the corresponding touch key data memory. The whole auto scan operation will sequentially be carried out in the above specific way from time slot 0 to time slot 3. After four keys are scanned, the TKRCOV bit will be set high and the TKBUSY bit will be set low. At the end of the auto scan mode, the first reference oscillator internal capacitor value will again be read from the touch key data memory and loaded into the corresponding TKMnROH/TKMnROL registers. Then the 16-bit C/F counter value will again be written into the relevant touch key data memory. Touch Key Data Memory Each of the devices provides two dedicated Data Memory area for the touch key auto scan mode. One area is used to store the 16-bit C/F counter values of the touch key module 0~n and located in Data Memory Sector 5. The other area is used to store the reference oscillator internal capacitor values of the touch key module 0~n and located in Data Memory Sector 6. Rev. 1.40 �33 De�e��e� 1�� �01�...
  • Page 234 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver 16-bit C/F counter value Ref. OSC Capacitor value (Sector 5) (Sector 6) TKM016DL_K1 TKM0ROL_K1 TKM016DH_K1 TKM0ROH_K1 TKM016DL_K2 TKM0ROL_K2 TKM016DH_K2 TKM0ROH_K2 Module 0 TKM016DL_K3 TKM0ROL_K3 TKM016DH_K3 TKM0ROH_K3 TKM016DL_K4 TKM0ROL_K4 TKM016DH_K4 TKM0ROH_K4 TKM116DL_K1...
  • Page 235 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Touch Key Scan Operation Flow Chart Sta�t W�ite Ref. OSC Capa�ito� to TKMnROH/TKMnROL Tou�h Key Manual S�an Ope�ation Sta�t Set Sta�t �it TKST 0 Busy flag TKBUSY=1 Initiate Ti�e Slot &...
  • Page 236 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Sta�t W�ite Ref. OSC inte�nal Capa�ito� value to Data Me�o�y (Se�to� � ) Tou�h Key Auto S�an Ope�ation Sta�t Set Sta�t �it TKST 0 Busy flag TKBUSY=1 Load Ref. OSC inte�nal Capa�ito�...
  • Page 237 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Touch Key Interrupt The touch key only has single interrupt, when the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. The 16-bit C/F counter, 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot counter in all modules will be automatically cleared. More details regarding the touch key interrupt is located in the interrupt section of the datasheet. Progrsmming Considerations After the relevant registers are setup, the touch key detection process is initiated the changing the TKST Bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV flag which is the time slot counter flag will go high when the counter overflows. When this happens an interrupt signal will be generated. When the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency. Rev. 1.40 �37...

  • Page 238: Low Voltage Detector - Lvd

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, V , and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the V voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Name — — LVDO LVDEN VBGEN VLVD�...

  • Page 239: Lvd Ope�Ation

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, V , with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, V , falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay t should be allowed for the circuitry to stabilise before reading the LVDS LVDO bit. Note also that as the V voltage may rise and fall rather slowly, at the voltage nears that of V , there may be multiple bit LVDO transitions. V D D L V D L V D E N L V D O...

  • Page 240: Interrupts

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. These devices contain several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0 and INT1 pins, while the internal interrupts are generated by various internal functions such as the TMs, Touch Key Module, Time Base, LVD, EEPROM, SIM, UART and the A/ D converter, etc. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain...
  • Page 241 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Register Name INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — TKMF INT1F INT0F TKME INT1E INT0E INTC1 MF1F MF0F MF1E MF0E INTC2 MF3F TB1F TB0F MF�F MF3E TB1E TB0E MF�E...
  • Page 242 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver INTC0 Register Name — TKMF INT1F INT0F TKME INT1E INT0E — — Bit 7 Unimplemented, read as “0” TKMF: Touch key interrupt request flag Bit 6 0: No request 1: Interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4 INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request Bit 3 TKME: Touch key interrupt control 0: Disable 1: Enable Bit 2...
  • Page 243 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver INTC1 Register Name MF1F MF0F MF1E MF0E Bit 7 ADF: A/D Converter interrupt request flag 0: No request 1: Interrupt request Bit 6 MF1F: Multi-function 1 interrupt request flag 0: No request 1: Interrupt request Bit 5 MF0F: Multi-function 0 interrupt request flag 0: No request 1: Interrupt request Bit 4 URF: UART transfer interrupt request flag 0: No request 1: Interrupt request Bit 3 ADE: A/D Converter interrupt control 0: Disable 1: Enable Bit 2 MF1E: Multi-function 1 interrupt control 0: Disable 1: Enable...
  • Page 244 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver INTC2 Register Name MF3F TB1F TB0F MF�F MF3E TB1E TB0E MF�E Bit 7 MF3F: Multi-function 3 interrupt request flag 0: No request 1: Interrupt request Bit 6 TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 5 TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 4 MF2F: Multi-function 2 interrupt request flag 0: No request 1: Interrupt request Bit 3 MF3E: Multi-function 3 interrupt control 0: Disable 1: Enable...
  • Page 245 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver MFI1 Register Name STMAF STMPF CTM1AF CTM1PF STMAE STMPE CTM1AE CTM1PE Bit 7 STMAF: STM Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 6 STMPF: STM Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 5 CTM1AF: CTM1 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4 CTM1PF: CTM1 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3 STMAE: STM Comparator A match Interrupt control 0: Disable 1: Enable...
  • Page 246 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver MFI2 Register Name — SIMF PTMAF PTMPF — SIME PTMAE PTMPE — — — — Bit 7 Unimplemented, read as “0” SIMF: SIM Interrupt request flag Bit 6 0: No request 1: Interrupt request Bit 5 PTMAF: PTM Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4 PTMPF: PTM Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as “0”...
  • Page 247 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A or A/D conversion completion, etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred.

  • Page 248: Inte

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Legend EMI auto disa�led in ISR Request Flag� no auto �eset in ISR Request Flag� auto �eset in ISR Inte��upt Request Ena�le Maste� P�io�ity Vector Name Flags Bits Ena�le Ena�le Bits...
  • Page 249 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Touch Key Interrupt For a Touch Key interrupt to occur, the global interrupt enable bit, EMI, and the Touch Key interrupt enable TKME must be first set. An actual Touch Key interrupt will take place when the Touch Key request flag, TKMF, is set, a situation that will occur when the time slot counter overflows. When the interrupt is enabled, the stack is not full and the Touch Key time slot counter overflow occurs, a subroutine call to the relevant touch key interrupt vector, will take place. When the interrupt is serviced, the Touch Key interrupt request flag, TKMF, will be automatically reset and the EMI Bit will be automatically cleared to disable other interrupts. UART Transfer Interrupt The UART Transfer Interrupt is controlled by several UART transfer conditions. When one of these conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and UART Interrupt enable bit, URE, must first be set. When the interrupt is enabled, the stack is not full and any of the...
  • Page 250 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Time Base Interrupt The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its internal timer. When this happens its interrupt request flag, TBnF, will be set. To allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to its respective vector location will take place. When the interrupt is serviced, the interrupt request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, f or f , originates from the internal clock source f /4 or f and then...
  • Page 251 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver TB0C Register Name TB0ON — — — — TB0� TB01 TB00 — — — — — — — — Bit 7 TB0ON: Time Base 0 Enable Control 0: Disable 1: Enable Bit 6~3 Unimplemented, read as “0” Bit 2~0 TB02~TB00: Time Base 0 time-out period selection 000: 2 PSC0 001: 2 PSC0...
  • Page 252 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface, an I C slave address match or I C bus time-out occurrence. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the Serial Interface Interrupt enable bit, SIME, and Muti-function interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and any of the above described situations occurs, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program...
  • Page 253 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though these devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an...

  • Page 254: Application Circuits

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Application Circuits Analog Signals KEY1 � SPI/I Co��uni�ation Devi�e RS_DIR KEYx 32768Hz RS488 Transceiver COM0~COM3 OSC1 SEGx Syste� C�ystal OSC� PWM / Capture Buzzer 0.1µF 10µF Cont�ol Devi�e BS67F3x0 Rev. 1.40 ��4...

  • Page 255: Instruction Set

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to...

  • Page 256: Bit Ope�Ations

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such...

  • Page 257: Instruction Set Summary

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A�[�] Add Data Me�o�y to ACC Z� C� AC� OV� SC ADDM A�[�] Add ACC to Data Me�o�y...
  • Page 258 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Mnemonic Description Cycles Flag Affected Data Move MOV A�[�] Move Data Me�o�y to ACC None MOV [�]�A Move ACC to Data Me�o�y Note None MOV A�x Move i��ediate data to ACC...

  • Page 259: Extended Inst�U�Tion Set

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Arithmetic LADD A�[�] Add Data Me�o�y to ACC �...
  • Page 260 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Mnemonic Description Cycles Flag Affected Branch LSZ [�] Skip if Data Memory is zero � Note None LSZA [�] Skip if Data Memory is zero with data movement to ACC �...

  • Page 261: Instruction Definition

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Instruction Definition Add Data Memory to ACC with Carry ADC A,[m] Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s)
  • Page 262 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None...
  • Page 263 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ← [m] − 1 Affected flag(s) DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ← [m] − 1 Affected flag(s) Enter power down mode HALT Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO ← 0 PDF ← 1 Affected flag(s) TO, PDF INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1.
  • Page 264 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ [m] Affected flag(s) Logical OR immediate data to ACC OR A,x Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ x Affected flag(s) ORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
  • Page 265 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 Affected flag(s) None Rotate Data Memory left through Carry RLC [m] Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 Affected flag(s) RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ← [m].i; (i=0~6)
  • Page 266 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 Affected flag(s) SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] − C Affected flag(s) OV, Z, AC, C, SC, CZ Subtract immediate data from ACC with Carry SBC A, x Description The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
  • Page 267 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver SET [m] Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ← 1 Affected flag(s) None SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] + 1 Skip if [m]=0 Affected flag(s) None...
  • Page 268 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − x Affected flag(s) OV, Z, AC, C, SC, CZ SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 ↔ [m].7~[m].4 Affected flag(s) None...
  • Page 269 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver TABRD [m] Read table (specific page) to TBLH and Data Memory Description The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None ITABRD [m] Increment table pointer low byte first and read table to TBLH and Data Memory Description Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte)

  • Page 270: Extended Instruction Definition

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC LADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC LADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m]...
  • Page 271 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LCPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] ← [m] Affected flag(s) LCPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) LDAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition.
  • Page 272 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LMOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None LMOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] ← ACC Affected flag(s) None LOR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ [m] Affected flag(s) LORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
  • Page 273 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LRR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 Affected flag(s) None LRRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None LRRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0...
  • Page 274 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LSDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] − 1 Skip if [m]=0 Affected flag(s) None LSDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None LSET [m] Set Data Memory Description Each bit of the specified Data Memory is set to 1.
  • Page 275 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LSNZ [m] Skip if Data Memory is not 0 Description If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m] ≠ 0 Affected flag(s) None LSUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ LSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m]...
  • Page 276 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver LSZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i=0 Affected flag(s) None LTABRD [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LTABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte)

  • Page 277: Package Information

    BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.40 �77 De�e��e� 1�� �01�...
  • Page 278 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver 48-pin LQFP (7mm×7mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.3�4 BSC — — 0.�7� BSC — — 0.3�4 BSC — — 0.�7� BSC — — 0.0�0 BSC —...
  • Page 279 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver 64-pin LQFP (7mm×7mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.3�4 BSC — — 0.�7� BSC — — 0.3�4 BSC — — 0.�7� BSC — — 0.01� BSC —...
  • Page 280 BS67F340/BS67F350/BS67F360/BS67F370 Enhanced Touch A/D Flash MCU with LCD Driver 80-pin LQFP (10mm×10mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.47� BSC — — 0.394 BSC — — 0.47� BSC — — 0.394 BSC — — 0.01�7 BSC —...
  • Page 281 However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that su�h appli�ations will �e suita�le without fu�the� �odifi�ation� no� �e�o��ends the use of its p�odu�ts fo�...

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