I/O Pin Structures; Programming Considerations - Holtek BS86DH12C Manual

• IFS1 Register
Bit 7
Name —
R/W —
POR —
Bit 7~4 Unimplemented, read as "0"
PTPIPS: PTPI input source pin selection
Bit 3
0: PA6
1: PA3
Bit 2 PTCKPS: PTCK input source pin selection
0: PA1
1: PA7
Bit 1 CTCK1PS: CTCK1 input source pin selection
0: PA6
1: PB1
Bit 0 CTCK0PS: CTCK0 input source pin selection
0: PA7
1: PB0

I/O Pin Structures

The accompanying diagram illustrates the internal structure of the I/O logic function. As the exact
logical construction of the I/O pin will differ from this drawing, it is supplied as a guide only to
assist with the functional understanding of the I/O logic function. The wide range of pin-shared
structures does not permit all types to be shown.
Write Control Register
Read Control Register
Write Data Register
Read Data Register

Programming Considerations

Within the user program, one of the things first to consider is port initialisation. After a reset,
all of the I/O data and port control registers will be set high. This means that all I/O pins will be
defaulted to an input state, the level of which depends on the other connected circuitry and whether
pull-high selections have been chosen. If the port control registers are then programmed to set some
pins as outputs, these output pins will have an initial high output value unless the associated port
Rev. 1.00
High Voltage Touch A/D Flash MCU with HVIO
6 5
— —
— —
— —
Control Bit
Data Bus D Q
CK Q
S
Chip Reset
Data Bit
D Q
CK Q
S
M
System Wake-up
Logic Function Input/Output Structure
72
4 3 2
— PTPIPS PTCKPS CTCK1PS CTCK0PS
— R/W R/W
— 0 0
V
DD
Pull-high
Register Weak
Select
Pull-up
U
X
PA only
wake-up Select
BS86DH12C
1 0
R/W R/W
0 0
I/O pin
October 26, 2018