Intel Xeon Design Manual page 5

17 Single Channel Source Clocked Signal Group Routing Guidelines............................................37
18 Single Channel Chip Select Routing Guidelines.........................................................................38
19 Single Channel Clock Enable Routing Guidelines......................................................................39
20 Single Channel Receive Enable Routing Guidelines..................................................................40
21 DDRCOMP Routing Guidelines..................................................................................................41
22 DDRCVO Routing Guidelines.....................................................................................................42
Revision History
Date
July 2003
January 2003
June 2002
January 2002
Platform Design Guide Addendum
Revision
Updated memory interface routing information and added Low
-004
Voltage Intel
Updated and expanded memory interface routing information.
-003
Added E7501 chipset information.
-002 Document Update
-001 Initial Release
Description
®
TM
Xeon processor information.
Contents
5