Intel Xeon Design Manual page 4

Contents
Figures
1 Uni-processor System Bus Topology ......................................................................................... 10
2 Topology for Asynchronous GTL+ Signals Driven by the Processor.......................................... 15
3 FERR# Routing Topology for Low Voltage Intel
1 Recommended THERMTRIP# Circuit ........................................................................................ 16
4 Topology for Asynchronous GTL+ Signals Driven by the Chipset.............................................. 17
5 INIT# Routing Topology for a Uni-processor System ................................................................. 18
6 Voltage Translator Circuit ........................................................................................................... 18
7 BR[3:0]# Connection for UP Configuration................................................................................. 19
8 DIMM Connector Styles Supported ............................................................................................ 22
9 1-DIMM per Channel Implementation......................................................................................... 23
10 2-DIMMs per Channel Implementation....................................................................................... 23
11 Dual Channel 2-DIMM Command Clock Topology..................................................................... 26
12 1-DIMM Per Channel Decoupling ............................................................................................... 29
13 2-DIMMs Per Channel Decoupling ............................................................................................. 30
14 Single Channel 2-DIMM Implementation .................................................................................... 31
15 Single Channel 4-DIMM Implementation .................................................................................... 31
16 Single Channel Source Synchronous Topology DIMM Solution ................................................ 35
17 Trace Length Matching Requirements for Single Channel Source Synchronous Routing ......... 35
18 Single Channel 2-DIMM Command Clock Topology .................................................................. 36
19 SIngle Channel Source Clocked Signal Topology ...................................................................... 37
20 Single Channel Chip Select Topology ........................................................................................ 38
21 Single Channel CKE Topology ................................................................................................... 39
22 Single Channel Receive Enable Signal Routing Guidelines....................................................... 40
23 Single Channel DDRCOMP Resistive Compensation ................................................................ 41
24 Single Channel DDRCVO Single Channel Routing Guidelines .................................................. 42
25 Single Channel 2-DIMM Decoupling .......................................................................................... 43
26 Single Channel 4-DIMM Decoupling .......................................................................................... 44
Tables
1 Reference Documents .................................................................................................................. 7
2 System Bus Signal Groups........................................................................................................... 9
3 Uni-processor System Bus Routing Summary ........................................................................... 10
4 2X and 4X Signal Groups ........................................................................................................... 11
5 Source Synchronous Signals and Associated Strobes .............................................................. 11
6 Common Clock Signals .............................................................................................................. 13
7 Asynchronous GTL+ and Miscellaneous Signals ....................................................................... 14
8 Dual Channel Source Synchronous Signal Group Routing Guidelines ...................................... 24
9 Dual Channel Command Clock Pair Routing Guidelines ........................................................... 25
10 Dual Channel Source Clocked Signal Group Routing Guidelines .............................................. 26
11 Dual Channel Chip Select Routing Guidelines ........................................................................... 27
12 Dual Channel Clock Enable Routing Guidelines ........................................................................ 28
13 Channel B Signal Terminations .................................................................................................. 32
14 Single Channel DQ/CB to DQS Mapping ................................................................................... 32
15 Single Channel Source Synchronous Signal Group Routing Guidelines ................................... 34
16 Single Channel Command Clock Pair Routing Guidelines ......................................................... 36
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Xeon™ Processors....................................... 16
Platform Design Guide Addendum