Interrupt Control; I Flag; Ir Bit - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupts

5.2 Interrupt Control

This section explains how to enable/disable maskable interrupts and set acknowledge priority. The expla-
nation here does not apply to non-maskable interrupts.
Maskable interrupts are enabled and disabled by using the I flag, IPL, and bits ILVL2 to ILVL0 in each
interrupt control register. Whether or not an interrupt is requested is indicated by the IR bit in each interrupt
control register.
For details about the memory allocation and the configuration of interrupt control registers, refer to the
R8C's hardware manual.

5.2.1 I Flag

The I flag is used to disable/enable maskable interrupts. When the I flag is set to 1 (enabled), all
maskable interrupts are enabled; when the I flag is cleared to 0 (disabled), they are disabled.
When the I flag is changed, the altered flag status is reflected in determining whether or not to accept an
interrupt request with the following timing:
• If the flag is changed by an REIT instruction, the changed status takes effect beginning with the
REIT instruction.
• If the flag is changed by an FCLR, FSET, POPC, or LDC instruction, the changed status takes
effect beginning with the next instruction.
When changed by REIT instruction
Interrupt request generated
When changed by FCLR, FSET, POPC, or LDC instruction
Interrupt request generated
Figure 5.2.1 Timing with Which Changes of I Flag are Reflected in Interrupt Handling

5.2.2 IR Bit

The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. The IR bit is cleared to
0 (interrupt not requested) after the interrupt request is acknowledged and the program branches to the
corresponding interrupt vector.
The IR bit can be cleared to 0 by a program. Do not set it to 1.
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Determination whether or not to
accept interrupt request
Previous
REIT
instruction
(If I flag is changed from 0 to 1 by REIT instruction)
Previous
FSET I
instruction
(If I flag is changed from 0 to 1 by FSET instruction)
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Interrupt sequence
Determination whether or not to
accept interrupt request
Interrupt sequence
Next instruction
5.2 Interrupt Control
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