Ilvl2 To Ilvl0 Bis, Ipl - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupts

5.2.3 ILVL2 to ILVL0 bis, IPL

Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 5.2.1 shows how interrupt priority levels are set. Table 5.2.2 shows interrupt enable levels in
relation to IPL.
The following lists the conditions under which an interrupt request is acknowledged:
• I flag
• IR bit
• Interrupt priority level
The I flag, bits ILVL2 to ILVL0, and IPL are independent of each other, and they do not affect each other.
Table 5.2.1 Interrupt Priority Levels
ILVL2–ILVL0
Level 0 (interrupt disabled)
000
2
Level 1
001
2
010
Level 2
2
011
Level 3
2
Level 4
100
2
Level 5
101
2
110 Level 6
2
Level 7
111
2
When the IPL or the interrupt priority level of an interrupt is changed, the altered level is reflected in
interrupt handling with the following timing:
• If the IPL is changed by an REIT instruction, the new level takes effect beginning with the instruction
that is executed two clock cycles after the last clock cycle of the REIT instruction.
• If the IPL is changed by a POPC, LDC, or LDIPL instruction, the new level takes effect beginning with
the instruction that is executed three clock cycles after the last clock cycle of the instruction used.
• If the interrupt priority level of a particular interrupt is changed by an instruction such as MOV, the
new level takes effect beginning with the instruction that is executed two or three clock cycles after the
last clock cycle of the instruction used.
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
= 1
= 1
> IPL
Interrupt Priority Priority
Level
Low
High
page 250 of 263
Table 5.2.2 Interrupt Priority Levels Enabled by IPL
IPL
Interrupt levels 1 and above are enabled.
000
2
Interrupt levels 2 and above are enabled.
001
2
Interrupt levels 3 and above are enabled.
010
2
Interrupt levels 4 and above are enabled.
011
2
Interrupt levels 5 and above are enabled.
100
2
Interrupt levels 6 and above are enabled.
101
2
Interrupt levels 7 and above are enabled.
110
2
All maskable interrupts are disabled.
111
2
5.2 Interrupt Control
Enabled interrupt priority
levels