Note On Interrupts; Reading Address 0000016; Sp Setting; Modifying Interrupt Control Register - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupts

5.7 Note on Interrupts

5.7.1 Reading Address 00000
Avoid reading address 00000
reads interrupt information (interrupt number and interrupt request priority level) from address 00000
during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to 0.
If address 00000
the enabled interrupts is set to 0. This may cause the interrupt to be canceled or an unexpected interrupt
to be generated.

5.7.2 SP Setting

Set a value in SP before accepting an interrupt. SP is set to 0000
is accepted before setting a value in SP, the program may go out of control.
5.7.3 Changing Interrupt Control Register
(1) Individual interrupt control registers can only be modified while no interrupt requests corresponding
to that register are generated. If interrupt requests managed by an interrupt control register are likely
to occur, disable interrupts before changing the contents of the interrupt control register.
(2) When modifying an interrupt control register after disabling interrupts, care must be taken when
selecting the instructions to be used.
Changing Bits Other Than IR Bit
If an interrupt request corresponding to the register is generated while executing the instruction, the IR
bit may not be set to 1 (interrupt requested), with the result that the interrupt request is ignored. To get
around this problem, use the following instructions to modify the register: AND, OR, BCLR, BSET.
When Changing IR Bit
Even when the IR bit is cleared to 0 (interrupt not requested), it may not actually be cleared to 0 depend-
ing on the instruction used. Therefore, use the MOV instruction to set the IR bit to 0.
(3) When disabling interrupts using the I flag, refer to the following sample programs. (Refer to (2) above
regarding changing interrupt control registers in the sample programs.)
Sample programs 1 to 3 are to prevent the I flag from being set to 1 (interrupt enabled) before writing to
the interrupt control registers depending on the state of the internal bus or the instruction queue buffer.
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
16
in a program. When a maskable interrupt request is accepted, the CPU
16
is read in a program, the IR bit for the interrupt which has the highest priority among
16
page 259 of 263
5.7 Notes on Interrupts
after reset. Therefore, if an interrupt
16
16