Interrupt Sequence - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupts

5.3 Interrupt Sequence

The interrupt sequence — the operations performed from the instant an interrupt is accepted to the instant
the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed and transfers control to the interrupt sequence from the next cycle.
If an interrupt occurs during execution of the SMOVB, SMOVF, SSTR, or RMPA instruction, the processor
temporarily suspends the instruction being executed and transfers control to the interrupt sequence.
In the interrupt sequence, the processor carries out the operations listed below. Figure 5.3.1 shows the
interrupt sequence execution time.
(1) The CPU obtains the interrupt information (the interrupt number and interrupt request level) by reading
address 00000
16
issued).
(2) The FLG register is saved as it was immediately before the start of the interrupt sequence in a tempo-
rary register 1 within the CPU.
(3) The I flag, the D flag, and the U flag in the FLG register are set as follows:
• The I flag is cleared to 0 (interrupts disabled)
• The D flag is cleared to 0 (single-step interrupt disabled)
•The U flag is cleared to 0 (ISP specified)
However, the U flag status does not change when the INT instruction for software interrupt numbers 32 to
63 is executed.
(4) The contents of the temporary register
(5) The PC is saved in the stack area.
(6) The interrupt priority level of the accepted instruction is set in IPL.
(7) The first address of the interrupt routine set to the interrupt vector is set in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the starting
address of the interrupt routine.
Note 1: This register cannot be accessed by the user.
1 2
C P U c l o c k
A d d r e s s
A d d r e s s b u s
0 0 0 0 0
I n t e r r u p t
D a t a b u s
i n f o r m a t i o n
R D
W R
N o t e : U n d e f i n e d p a r t s d i f f e r a c c o r d i n g t o t h e s t a t e s o f t h e q u e u e b u f f e r .
I f t h e q u e u e b u f f e r i s i n a s t a t e w h e r e a n i n s t r u c t i o n c a n b e a c c e p t e d , a r e a d
c y c l e i s g e n e r a t e d .
Figure 5.3.1 Interrupt Sequence Executing Time
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
. Then, the IR bit corresponding to the interrupt is set to 0 (interrupt not requested
1
3 4 5 6 7
U n d e f i n e d
1 6
Undefined
U n d e f i n e d
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are saved within the CPU in the stack area.
8 9 1 0 11 1 2
SP-4 SP-3
S P - 2 S P - 1
S P - 2
SP-1 S P - 4
c o n t e n t s
contents c o n t e n t s
5.3 Interrupt Sequence
13 1 4 15 1 6 1 7
V E C V E C + 1 V E C + 2
SP-3 V E C V E C + 1
contents c o n t e n t s c o n t e n t s
1 8
1 9 2 0
PC
V E C + 2
c o n t e n t s