Interrupt Priority - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupts

5.5 Interrupt Priority

If two or more interrupt requests occur while a single instruction is being executed, the interrupt request that
has higher priority is acknowledged.
The priority level of maskable interrupts (peripheral functions) can be selected arbitrarily by setting bits
ILVL2 to ILVL0. If multiple maskable interrupts are assigned the same priority level, the priority that is set in
hardware determines which is acknowledged.
Special interrupts such as the watchdog timer interrupt have their priority levels set in hardware. Figure
5.5.1 lists the interrupt priority levels of hardware interrupts.
Software interrupts are not affected by interrupt priority. They always cause control to branch to an interrupt
routine when the relevant instruction is executed.
Figure 5.5.1 Interrupt Priority Levels of Hardware Interrupts
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Watchdog timer
Oscillation stop detection
Peripheral function
Single-step
Address match
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Reset
5.5 Interrupt Priority
High
Low