Changing Interrupt Control Register - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupts
5.2.4 Changing Interrupt Control Registers
(1) Individual interrupt control registers can only be modified while no interrupt requests corresponding
to that register are generated. If interrupt requests managed by the interrupt control register are
likely to occur, disable interrupts before changing the contents of the interrupt control register.
(2) When modifying an interrupt control register after disabling interrupts, care must be taken when
selecting the instructions to be used.
Changing Bits Other Than IR Bit
If an interrupt request corresponding to the register is generated while executing the instruction, the IR
bit may not be set to 1 (interrupt requested), with the result that the interrupt request is ignored. To get
around this problem, use the following instructions to modify the register: AND, OR, BCLR, BSET.
Changing IR Bit
Even when the IR bit is cleared to 0 (interrupt not requested), it may not actually be cleared to 0 depend-
ing on the instruction used. Therefore, use the MOV instruction to set the IR bit to 0.
(3) When disabling interrupts using the I flag, refer to the following sample programs. (Refer to (2) above
regarding changing interrupt control registers in the sample programs.)
Sample programs 1 to 3 are to prevent the I flag from being set to 1 (interrupt enabled) before writing to
the interrupt control registers depending on the state of the internal bus or the instruction queue buffer.
Example 1: Use NOP instruction to prevent I flag being set to 1
INT_SWITCH1:
FCLR
AND.B
NOP
NOP
FSET
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR
AND.B
MOV.W MEM, R0
FSET
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR
AND.B
POPC
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
before interrupt control register is changed
I ; Disable interrupts
#00H, 0056H ; Set TXIC register to 00
I ; Enable interrupts
I ; Disable interrupts
#00H, 0056H ; Set TXIC register to 00
; Dummy read
I ; Enable interrupts
I ; Disable interrupts
#00H, 0056H ; Set TXIC register to 00
FLG ; Enable interrupts
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5.2 Interrupt Control
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