Instruction Queue Buffer - Renesas R8C/Tiny Series Software Manual

Chapter 6 Calculating the Number of Cycles

6.1 Instruction Queue Buffer

R8C/Tiny Series microcomputers have 4-stage (4-byte) instruction queue buffers. If the instruction queue
buffer has free space when the CPU can use the bus, instruction codes are taken into the instruction queue
buffer. This is referred to as "prefetching". The CPU reads (fetches) the instruction codes from the instruc-
tion queue buffer as it executes a program.
The explanation of the number of cycles in chapter 4 assumes that all the necessary instruction codes are
placed in the instruction queue buffer, and that 8-bit data is read or written to the memory without software
wait states. In the following cases, more cycles may be needed than the number of cycles indicated in this
manual:
• If not all of the instruction codes needed by the CPU have been placed in the instruction queue buffer.
Instruction codes are read in until all of the instruction codes required for program execution are avail-
able. Furthermore, the number of read cycles increases in the following case:
(1) The number of read cycles increases to match the number of wait cycles incurred when reading
instruction codes from an area in which software wait cycles exist.
• When reading or writing data to an area in which software wait cycles exist.
The number of read or write cycles increases to match the number of wait cycles incurred.
• When reading or writing 16-bit data from/to the SFR or the internal memory.
The memory is accessed twice to read or write one 16-bit data item. Therefore, the number of read or
write cycles increases by one for each 16-bit data item read or written.
Note that if prefetch and data access occur at the same time, data access has priority. Also, if more than
three bytes of instruction codes exist in the instruction queue buffer, the CPU assumes there is no free
space and, therefore, does not prefetch instruction code.
Figure 6.1.1 shows an example of starting a read instruction (without software wait).
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
page 262 of 263
6.1 Instruction Queue Buffer