Software Interrupts - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupts
Table 5.1.1 Interrupt Sources (Nonmaskable) and Fixed Vector Tables
Interrupt Source
Undefined Instruction
Overflow
BRK Instruction
Address Match
1
Single Step
Watchdog Timer•Oscil-
lation Stop Detection
(Reserved)
(Reserved)
Reset
Note 1: This is a dedicated interrupt used by development support tools. Do not use this interrupt.

5.1.2 Software Interrupts

Software interrupts are generated by an instruction that generates an interrupt request when executed.
Software interrupts are nonmaskable.
Undefined-instruction interrupt
This interrupt occurs when the UND instruction is executed.
Overflow interrupt
This interrupt occurs if the INTO instruction is executed when the O flag is set to 1 (arithmetic result is
overflow).
The instructions that cause the O flag to change are as follows: ABS, ADC, ADCF, ADD, CMP, DIV,
DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB.
BRK interrupt
This interrupt occurs when the BRK instruction is executed.
INT instruction interrupt
This interrupt occurs when the INT instruction is executed. The software interrupt numbers which can be
specified by the INT instruction are 0 to 63. Note that software interrupt numbers 4 to 31 are assigned to
peripheral function interrupts. This means that it is possible to execute the same interrupt routines used
by peripheral function interrupts by executing the INT instruction.
For software interrupt numbers 0 to 31, the U flag is saved when the INT instruction is executed and the
U flag is cleared to 0 to choose the interrupt stack pointer (ISP) before executing the interrupt sequence.
The U flag before the interrupt occurred is restored when control returns from the interrupt routine. For
software interrupt numbers 32 to 63, when the instruction is executed, the U flag does not change and the
SP selected at the time is used.
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Vector Table Addresses
Address (L) to Address (H)
0FFDC to 0FFDF
16
0FFE0 to 0FFE3
16
0FFE4 to 0FFE7
16
0FFE8 to 0FFEB
16
0FFEC to 0FFEF
16
0FFF0 to 0FFF3
16
0FFF4 to 0FFF7
16
0FFF8 to 0FFFB
16
0FFFC to 0FFFF
16
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Interrupt generated by the UND instruction.
16
Interrupt generated by the INTO instruction.
16
Executed beginning from address indicated by vector in
16
variable vector table if 0FFE7
FF .
16
16
Can be controlled by an interrupt enable bit.
16
Do not use this interrupt.
16
16
16
16
5.1 Outline of Interrupts
Description
address contents are
16