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SetTrigHndlr
Local Command Set 4-52
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43
44 to 49
50
51
60
61
and the value of <mode> specifies the signal
conditioning mode (where 0 = no conditioning). The
conditioning effects for bits 0 to 3 are as follows:
Bit
0
1
2
3
Response:
Program response: 0
Console response:
Mapping complete (line = <line text
source> mapped to line = <line text
destination>,
where the meaning of <line text source> and
<line text destination> correspond to the
value of <srcTrig> and <destTrig> as
follows:
Value of <srcTrig> Value of <line text
source>
or <destTrig>
0 to 7
8 to 9
40 to 49
50
51
60
61
Example:
Map TTL line 4 to go out of the front panel with no
signal conditioning.
MapTrigTrig 4, 41, 0
Purpose:
Replace the current TTL/ECL trigger, counter, or
tick timer interrupt handler with a specified trigger
1260-00C User Manual
Connection to EXTCLK input pin
Hardware-dependent GPIOs 4 to 9
TIC counter pulse output (TCNTR)
TIC counter finished output (GCNTR)
TIC TICK1 tick timer output
TIC TICK2 tick timer output
Conditioning Effect
Synchronize with next CLK edge
Invert signal polarity
Pulse stretch to one CLK minimum
Use EXTCLK (not CLK10) for conditioning
mode = <mode>).<CRLF>
or <line text destination>
TTL <line>
ECL (<line> - 8)
GPIO (<line> - 40)
TCNTR
GCNTR
TICK1
TICK2
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