Table 3. Gmch Considerations For Universal Socket 370 Design; Table 4. Intel ® Ich2 Considerations For Universal Socket 370 Design - Intel 815EG Design Manual

Universal Socket 370 Design
Signal
Name or
Pin
Number
PICCLK
PWRGOOD
VTT
VTTPWRGD

Table 3. GMCH Considerations for Universal Socket 370 Design

Pin
Name/Number
SMAA[12]
®
Table 4. Intel ICH2 Considerations for Universal Socket 370 Design
Signal
PWROK
36
Function In
® ®
Intel Pentium III
Processor
(CPUID=068xh) and
® ®
Intel Celeron
Processor
(CPUID=068xh)
Requires 2.5 V Requires 2.0 V
Requires 2.5 V Requires 1.8 V
Requires 1.5 V Requires 1.25 V
Not used Input signal to future
0.13 micron socket 370
processors to indicate
that VID signals are
stable
Issue
New strap required for determining
®
Pentium III Processor
(CPUID=068xh) and Celeron
Processor (CPUID=068xh)
or
Future 0.13 micron socket 370
processors
Issue
GMCH and Intel CK-815 must not
sample BSEL[1:0] until VTTPWRGD
is asserted. The ICH2 must not
initialize before the Intel CK-815
clocks stabilize.
Function In Future
0.13 Micron Universal Socket 370 Design
Socket 370
Processors
Addition of FET switch to provide
proper voltage, controlled by
processor identification signal.
Addition of resistor-divider network
to provide 2.1V, which will satisfy
voltage tolerance requirements of
the Pentium III processor
(CPUID=068xh) and Celeron
processor (CPUID=068xh) as well
as future 0.13 micron socket 370
processors.
Modification to VTT generation
circuit to switch between 1.5 V or
1.25 V, controlled by processor
identification signal.
Addition of VTTPWRGD
generation circuit.
Implementation For
Universal Socket 370 Design
Addition of FET switch controlled by
processor identification signal.
®
Implementation For Universal
Motherboard Design
Addition of circuitry to have VTTPWRGD
gate PWROK from power supply to ICH2.
The ICH2 will hold the GMCH in reset until
VTTPWRGD asserted plus 20 ms time
delay to allow Intel CK-815 clocks to
stabilize.
®
Intel 815EG Chipset Platform Design Guide
R
Implementation for