Miscellaneous Checklist For 370-Pin Socket Processors - Intel 815EG Design Manual

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14.2.4

Miscellaneous Checklist for 370-Pin Socket Processors

Checklist Items
BCLK
BSEL0
BSEL1
CLKREF
CPUPRES#
DYN_OE
PICCLK
PICD[1:0]
PLL1, PLL2
RTTCTRL (S35)
SLEWCTRL (E27)
STPCLK# (AG35)
THERMDN,
THERMDP
VCC2.5
GTL_REF/
CMOSREF (AK22)
VCC
CORE
VID[25mV, 3:0]
VTTPWRGD
®
Intel 815EG Chipset Platform Design Guide
• Connect to clock generator. / 22–33 Ω series resistor (though OEM needs to
simulate based on driver characteristics). To reduce pin-to-pin skew, tie host
clock outputs together at the clock driver then route to the GMCH and
processor.
• Case 1 (66/100/133 MHz support): 1 k Ω pull-up resistor to 3.3 V. Connect to
CK815 SEL0 input. Connect to GMCH LMD29 pin via 10 k Ω series resistor.
• Case 2 (100/133 MHz support): 1 k Ω pull-up resistor to 3.3 V. Connect to
PWRGOOD logic such that a logic Low on BSEL0 negates PWRGOOD.
• 1 k Ω pull-up resistor to 3.3 V. Connect to CK815 REF pin via 10 k Ω series
resistor. Connect to GMCH LMD13 pin via 10 k Ω series resistor.
• Connect to divider on VCC2.5 or VCC3.3 to create 1.25 V reference with a
4.7 µ F decoupling capacitor. Resistor divider must be created from 1%
tolerance resistors. Do not use VTT as source voltage for this reference!
• Tie to ground. Leave as No Connect or connect to PWRGOOD logic to gate
system from powering on if no processor is present. If used, 1 k Ω to 10 k Ω
pull-up resistor to VCC
CMOS
• 1 k Ω pull-up resistor to VTT.
• See Section 11.5.
• 150 Ω pull-up resistor to VCC
• Low-pass filter on VCC
CORE
inductor in series with VCC
series 33 µ F capacitor to PLL2.
• 56 Ω ± 1% pull-down resistor to ground.
• 110 Ω ± 1% pull-down resistor to ground.
• Connect to ICH2.
• No Connect if not used. Otherwise, connect to thermal sensor using vendor
guidelines.
®
• No connect for Pentium
III processors
• Connect to a 1.0 V voltage divider derived from VCC
• 16 ea. (min.) 4.7 µ F in 1206 package all placed within the PGA370 socket
cavity.
• 8 ea. (min.) 1 µ F in 0612 package placed in the PGA370 socket cavity.
• Connect to on-board VR or VRM. 25mV should connect to VID25mV. For on-
board VR, 10 k Ω pull-up resistor to power solution-compatible voltage is
required (usually pulled up to input voltage of the VR). Some of these
solutions have internal pull-ups. Optional override (jumpers, ASIC, etc.) could
be used. May also connect to system monitoring device.
• Pull up to VTT through 1 k Ω resistor and connect to VTTPWRGD circuitry.
System Design Checklist
Recommendations
.
/Connect to ICH2.
CMOS
provided on motherboard. Typically a 4.7 µ H
is connected to PLL1, and then through a
CORE
CMOS
.
177