Intel 815EG Design Manual page 10

Figure 50. Schematic of RAMDAC Video Interface...........................................................90
Figure 51. Cross-Sectional View of a Four-Layer Board ...................................................91
Figure 52. Recommended RAMDAC Component Placement and Routing ......................92
Figure 53. Recommended RAMDAC Reference Resistor Placement and Connections ..93
Figure 54. Hub Interface Signal Routing Example ............................................................97
Figure 55. Single Hub Interface Reference Divider Circuit................................................99
Figure 56. Locally Generated Hub Interface Reference Dividers ......................................99
Figure 57. Intel
Figure 58. Combination Host-Side / Device-Side IDE Cable Detection ..........................106
Figure 59. Device-Side IDE Cable Detection...................................................................107
Figure 60. Connection Requirements for Primary IDE Connector...................................108
Figure 61. Connection Requirements for Secondary IDE Connector..............................109
Figure 62. Intel
Figure 63. CNR Interface.................................................................................................111
Figure 64. CDC_DN_ENAB# Support Circuitry for a Single Codec on Motherboard ......112
Figure 65. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade..........113
Figure 66. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard /
One-Codec on CNR .................................................................................................114
Figure 67. CDC_DN_ENAB# Support for Two-Codecs on Motherboard /
Two-Codecs on CNR ...............................................................................................114
Figure 68. Example Speaker Circuit................................................................................116
Figure 69. USB Data Signals...........................................................................................119
Figure 70. Example PIRQ Routing ..................................................................................120
Figure 71. SMBus/SMLink Interface................................................................................121
Figure 72. Unified VCC_Suspend Architecture ...............................................................123
Figure 73. Unified VCC
Figure 74. Mixed VCC_Suspend/VCC
Figure 75. PCI Bus Layout Example................................................................................125
Figure 76. External Circuitry for the ICH2 RTC ...............................................................126
Figure 77. Diode Circuit to Connect RTC External Battery..............................................128
Figure 78. RTCRST External Circuit for ICH2 RTC ........................................................129
Figure 79. RTC Power Well Isolation Control..................................................................130
Figure 80. Intel
Figure 81. Single-Solution Interconnect...........................................................................133
Figure 82. LOM/CNR Interconnect ..................................................................................134
Figure 83. LAN_CLK Routing Example ...........................................................................135
Figure 84. Trace Routing.................................................................................................137
Figure 85. Ground Plane Separation ...............................................................................138
Figure 86. Intel
Figure 87. Critical Dimensions for Component Placement..............................................143
Figure 88. Intel
Figure 89. Critical Dimensions for Component Placement..............................................146
Figure 90. Termination Plane ..........................................................................................148
Figure 91. Intel
Figure 92. Dual-Footprint LAN Connect Interface ...........................................................149
Figure 93. Dual-Footprint Analog Interface .....................................................................149
Figure 94. FWH VPP Isolation Circuitry ..........................................................................151
Figure 95. Platform Clock Architecture for a 2-DIMM Solution........................................154
Figure 96. Platform Clock Architecture for a 3-DIMM Solution........................................156
Figure 97. Clock Routing Topologies ..............................................................................157
Figure 98. Power Delivery Map........................................................................................164
Figure 99. Pull-Up Resistor Example ..............................................................................167
Figure 100. Example 1.85 V/3.3 V Power Sequencing Circuit ........................................170
Figure 101. V5REF/3.3 V Sequencing Circuitry ..............................................................171
10
®
ICH2 Decoupling Capacitor Layout.......................................................102
®
ICH2 AC '97- Codec Connection .........................................................110
Architecture.........................................................................123
CORE
CORE
®
ICH2 / LAN Connect Section ................................................................132
®
82562EH Termination ...........................................................................142
® ®
82562ET/Intel 82562EM Termination .................................................145
®
82562ET/82562EM Disable Circuit.......................................................148
Architecture .................................................124
®
Intel 815EG Chipset Platform Design Guide
R