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System Design Checklist
14.4.3
LAN Interface
Checklist Items
LAN_CLK
LAN_RXD[2:0]
LAN_TXD[2:0]
LAN_RSTSYNC
NOTES:
1.
2.
14.4.4
EEPROM Interface
Checklist Items
EE_DOUT
EE_DIN
14.4.5
FWH/LPC Interface
Checklist Items
FWH[3:0]/ LAD[3:0]
LDRQ[1:0]
14.4.6
Interrupt Interface
Checklist Items
PIRQ#[D:A]
180
• Connect to LAN_CLK on Platform LAN Connect Device.
• Connect to LAN_RXD on Platform LAN Connect Device. ICH2 contains
integrated 9 k Ω pull-up resistors on interface.
• Connect to LAN_TXD on Platform LAN Connect Device.
LAN connect interface can be left NC if not used. Input buffers internally terminated.
In the event of EMI problems during emissions testing (FCC Classifications) you may need to place
a decoupling cap (~470 pF) on each of the 4 LED pins. Reduces emissions attributed to LAN
subsystem.
• Prototype Boards should include a placeholder for a pull-down resistor on
this signal line, but do not populate the resistor. Connect to EE_DIN of
EEPROM or CNR Connector.
• Connected to EEPROM data input signal (input from EEPROM perspective
and output from ICH2 perspective).
• No extra circuitry required. Connect to EE_DOUT of EEPROM or CNR
Connector. ICH2 contains an integrated pull-up resistor for this signal.
• Connected to EEPROM data output signal (output from EEPROM
perspective and input from ICH2 perspective).
• No extra pull-ups required. ICH2 Integrates 24 k Ω pull-up resistors on these
signal lines.
• These signals require a pull-up resistor. The recommendation is a 2.7 k Ω
pull-up resistor to VCC5 or 8.2 k Ω to VCC3.3.
• In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6,
7, 9, 10, 11, 12, 14 or 15 as described in the ICH2 datasheet. Each PIRQx#
line has a separate Route Control Register.
• In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17,
PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19.
Recommendations
Recommendations
Recommendations
Recommendations
®
Intel
815EG Chipset Platform Design Guide
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