V/3.3 V Power Sequencing; Figure 100. Example 1.85 V/3.3 V Power Sequencing Circuit - Intel 815EG Design Manual

Power Delivery
13.4.2

1.85 V/3.3 V Power Sequencing

The ICH2 has two pairs of associated 1.85 V and 3.3 V supplies. These are {VCC1_85, VCC3_3}
and {VCCSus1_85, VCCSus3_3}. These pairs are assumed to power up and power down together.
The difference between the two associated supplies must never be greater than 2.0 V. The
1.85 V supply may come up before the 3.3 V supply without violating this rule (though this is
generally not practical in a desktop environment, since the 1.85 V supply is typically derived from
the 3.3 V supply by means of a linear regulator).
One serious consequence of violation of the 2 V Rule is electrical overstress of oxide layers,
resulting in component damage.
The majority of the ICH2 I/O buffers are driven by the 3.3 V supplies, but are controlled by logic
that is powered by the 1.85 V supplies. Thus, another consequence of faulty power sequencing
arises if the 3.3 V supply comes up first. In this case the I/O buffers will be in an undefined state
until the 1.85 V logic is powered up. Some signals that are defined as "Input-only" actually have
output buffers that are normally disabled, and the ICH2 may unexpectedly drive these signals if the
3.3 V supply is active while the 1.85 V supply is not.
Figure 100 shows an example power-on sequencing circuit that ensures the 2 V Rule is obeyed.
This circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.85 V supply tracks the 3.3 V
supply. The NPN transistor controls the current through PNP from the 3.3 V supply into the
1.85 V power plane by varying the voltage at the base of the PNP transistor. By connecting the
emitter of the NPN transistor to the 1.85 V plane, current will not flow from the 3.3 V supply into
1.85 V plane when the 1.85 V plane reaches 1.85 V.

Figure 100. Example 1.85 V/3.3 V Power Sequencing Circuit

When analyzing systems that may be "marginally compliant" to the 2 V Rule, pay close attention
to the behavior of the ICH2's RSMRST# and PWROK signals, since these signals control internal
isolation logic between the various power planes:
• RSMRST# controls isolation between the RTC well and the Resume wells.
• PWROK controls isolation between the Resume wells and Main wells
170
+3.3V
220
Q2
220 NPN
470
Intel
+1.85V
Q1
PNP
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815EG Chipset Platform Design Guide
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