Figure 48. Intel ® 815 Chipset Decoupling Example - Intel 815EG Design Manual

System Memory Design Guidelines
Yellow lines show layer two plane splits. (Printed versions of this document will show the layer-
two plane splits in the left-side, bottom, right-side, and upper-right-side quadrants enclosed in gray
lines.) Note that the layer 1 shapes do not cross the plane splits. The bottom shape is a VSS fill
over VddSDRAM. The left-side shape is a VSS fill over VddAGP. The larger upper-right-side
shape is a VSS fill over VddCORE.
Additional decoupling capacitors should be added between the DIMM connectors to provide a
current return path for the reference plane discontinuity created by the DIMM connectors
themselves. One 0.01 µF X7R capacitor should be added per every ten SDRAM signals.
Capacitors should be placed between the DIMM connectors and evenly spread out across the
SDRAM interface.
For debug purposes, four or more 0603 capacitor sites should be placed on the backside of the
board, evenly distributed under the 815EG chipset platform's system memory interface signal
field.
®
Figure 48. Intel 815 Chipset Decoupling Example
84
®
Intel 815EG Chipset Platform Design Guide
R