Future Designs Require Pull-Ups And Pull-Downs On Any Unused Input And I/O Pins; Support For P-Mos Kicker "On": Smaa[9] Is Strapped High By An Internal 50 Kω Pull-Up Resistor; Electrostatic Discharge Platform Recommendations - Intel 815EG Design Manual

General Design Considerations
2.2 Future Designs Require Pull-Ups and Pull-Downs
on Any Unused Input and I/O Pins
Any new 815EG platform Universal Socket 370 design should insure no input or I/O pin is left
floating. For example, the TVCLKIN/INT# pin on many current 815 designs is left floating. This
pin should be pulled up to 1.8 V by a weak pull-up resistor (8.2 kΩ to 10 kΩ) on any future
815EG Universal Socket 370 design.
2.3 Support For P-MOS Kicker "ON": SMAA[9] Is
Strapped High by an Internal 50 kΩ Ω Ω Ω Pull-Up Resistor
The PSB P-MOS Kicker circuit should be enabled on all new, future 82815EG Universal Socket
370 designs. Use of the P-MOS Kicker circuit improves PSB timings by improving AGTL and
AGTL+ signal flight time. The 82815EG SMAA[9] is strapped high through an internal 50 kΩ
pull-up resistor to enable the PSB P-MOS Kicker.
Existing 815 designs which have implemented the pull-down resistor circuit on the SMAA[9]
signal as shown in the 815 Customer Reference Board schematics and populated the resistor site to
over-ride the internal pull-up resistor, may depopulate the site to enable the P-MOS Kicker circuit.
This activity should be based on timing analysis of the specific platform.
P-MOS Kicker circuit "ON" is the recommended setting for 82815EG Universal Socket 370
designs using future 0.13 micron technology processors.
2.4

Electrostatic Discharge Platform Recommendations

Electrostatic discharge (ESD) into a system can lead to system instability, and possibly cause
functional failures when a system is in use. There are system level design methodologies that when
followed can lead to higher ESD immunity. Electromagnetic fields due to ESD are introduced into
a system through chassis openings such as the I/O back panel and PCI slots. These fields can
introduce noise into signals and cause the system to malfunction. One can reduce the potential for
issues at the I/O area by adding more ground plane on the motherboard around the I/O area. This
can lead to a higher ESD immunity.
Intel recommends that the I/O area on the top and bottom signal layers of a 4-layer motherboard
near the I/O back panel be filled with a ground fill as shown in Figures 1-4. In addition, a ground
fill cutout should be placed on the Vcc layer in the area where the ground fill is done on the top
and bottom layers. Intel recommends filling the I/O area as much as possible without effecting the
signal routing. The board designer should fill the entire I/O area along the board edge.
The spacing from the ground fill to other shapes/traces should be at least 20 mils. It is
recommended that these ground fill areas be connected to two chassis mounting holes (as seen in
Figure 2). This will allow ESD current to travel to the chassis instead of the board. Ground
stitching vias should be placed throughout the entire ground fill if possible. It is important that the
vias are placed along the board edge. Ground stitching vias for the ground fill should be 100-150
mils apart or less.
In conclusion, Intel recommends the following:
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Intel 815EG Chipset Platform Design Guide
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