Clock Driver Frequency Strapping - Intel 815EG Design Manual

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Clock Decoupling
Several general layout guidelines should be followed when laying out the power planes for the
CK815 clock generator, as follows:
• Isolate power planes to the each of the clock groups.
• Place local decoupling as close as possible to power pins, and connect with short, wide traces
and copper.
• Connect pins to appropriate power plane with power vias (larger than signal vias).
• Bulk decoupling should be connected to a plane with 2 or more power vias.
• Minimize clock signal routing over plane splits.
• Do not route any signals underneath the clock generator on the component side of the board.
• An example signal via is a 14 mil finished hole with a 24 mil to 26 mil path. An example
power via is an 18 mil finished hole with a 33 mil to 38 mil path. For large decoupling or
power planes with large current transients, a larger power via is recommended.
12.4

Clock Driver Frequency Strapping

A CK-815-compliant clock driver device uses two of its pins to determine whether processor clock
outputs should run at 133 MHz, 100 MHz or 66 MHz. The pin names are SEL0 and REF0. In
addition, a third strapping pin is defined (SEL1), which must be pulled High for normal clock
driver operation.
SEL0 and REF0 are driven by either the processor, which depends on the processor populated in
the 370-pin socket, or pull-up resistors on the motherboard. While SEL0 is a pure input to a CK-
815-compliant clock driver, REF0 is also the 14 MHz output that drives the ICH2 and other
devices on the platform. In addition to sampling BSEL[1:0] at reset, CK-815-compliant clock
drivers are configured by the BIOS via a two-wire interface to drive SDRAM clock outputs at
either 100 MHz (default) or 133 MHz (if all system requirements are met).
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Intel 815EG Chipset Platform Design Guide
Clocking
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