Page 1 ® Intel 815EG Chipset Platform For Use with Universal Socket 370 Design Guide August 2002 Document Number: 298301-002...
Page 2 Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Intel, Celeron, Pentium, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
Page 3: Table Of Contents
VTT Processor Pin AG1 ................40 4.2.5 Identifying the Processor at the GMCH..........41 4.2.6 Configuring Non-VTT Processor Pins ...........42 4.2.7 VCMOS Reference................43 4.2.8 Processor Signal PWRGOOD...............44 4.2.9 APIC Clock Voltage Switching Requirements ........45 4.2.10 GTLREF Topology and Layout..............46 ® Intel 815EG Chipset Platform Design Guide...
Page 4 5.12 Thermal Considerations..................72 5.12.1 Heatsink Volumetric Keep-Out Regions..........72 ® ® 5.12.2 Fan Heatsink Keep-Out Adherence for Future Boxed Intel Celeron Processors ....................74 5.13 Debug Port Changes ....................75 System Memory Design Guidelines...................77 System Memory Routing Guidelines..............77 System Memory 2-DIMM Design Guidelines ............78 6.2.1...
Page 5 AC ’97 Routing ..................116 11.3.5 Motherboard Implementation ..............117 11.4 USB........................118 11.4.1 Using Native USB Interface..............118 11.4.2 Disabling the Native USB Interface of ICH2........119 11.5 I/O APIC Design Recommendation ..............119 11.5.1 PIRQ Routing Example ...............120 ® Intel 815EG Chipset Platform Design Guide...
Page 6 11.10.1 In-Circuit FWH Programming..............151 11.10.2 FWH V Design Guidelines ...............151 11.10.3 FWH Decoupling .................152 Clocking ...........................153 12.1 2-DIMM Clocking ....................153 12.2 3-DIMM Clocking ....................155 12.3 Clock Routing Guidelines..................157 12.4 Clock Driver Frequency Strapping ..............159 ® Intel 815EG Chipset Platform Design Guide...
Page 7 14.4.10 Processor Signals ................184 14.4.11 System Management ................184 14.4.12 RTC ...................184 14.4.13 AC ’97 ...................185 14.4.14 Miscellaneous Signals .................186 14.4.15 Power ...................187 14.4.16 IDE Checklist..................188 14.5 LPC Checklist .....................190 14.6 System Checklist ....................191 ® Intel 815EG Chipset Platform Design Guide...
Page 8 14.7 FWH Checklist ....................191 14.8 Clock Synthesizer Checklist................192 14.9 System Memory Checklist ..................193 14.10 Power Delivery Checklist ..................193 Third-Party Vendor Information ..................195 ® Intel 815EG Chipset Platform Design Guide...
Page 9 ® Figure 22. Gating Power to Intel CK-815 .................47 ® Figure 23 PWROK Gating Circuit for Intel ICH2 ..............48 Figure 24. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)..52 Figure 25. AGTL/AGTL+ Trace Routing................53 Figure 26. Routing for THRMDP and THRMDN..............56 Figure 27.
Page 10 Figure 97. Clock Routing Topologies ................157 Figure 98. Power Delivery Map..................164 Figure 99. Pull-Up Resistor Example ................167 Figure 100. Example 1.85 V/3.3 V Power Sequencing Circuit ........170 Figure 101. V5REF/3.3 V Sequencing Circuitry ..............171 ® Intel 815EG Chipset Platform Design Guide...
Page 11 Table 32. Intel CK-815 (2-DIMM) Clocks...............153 ® Table 33. Intel CK-815 (3-DIMM) Clocks...............155 Table 34. Simulated Clock Routing Solution Space ............158 Table 35. Simulated Clock Skew Assumptions ...............160 Table 36. Power Delivery Definitions ................163 ® Intel 815EG Chipset Platform Design Guide...
Page 12 • Revised Section 13.4.3, 3.3V/V5REF Sequencing • Revised Checklist Recommendations for 5V_REF_SUS in Section 14.4.15, Power • Added SUSCLK to the RTC Checklist in Section 14.4.12 • Added Section 10.3 Power Supply PS_ON Considerations ® Intel 815EG Chipset Platform Design Guide...
Page 13: Introduction
82815E chipset: This chipset contains the Intel 82815E and the Intel 82801BA ICH2. ® • Intel 82815P chipset: This chipset contains the Intel 82815P and the 82801AA ICH. There is no internal graphics capability. This GMCH uses an AGP port only. ® • Intel 82815EP chipset: This chipset contains the Intel 82815EP and the 82801BA ICH2.
Page 14: Terminology
• Odd Mode Crosstalk–coupling from single or multiple aggressors when all the aggressors switch in the opposite direction that the victim is switching. GMCH Graphics and Memory Controller Hub. A component of the Intel 815 chipset platform for use with the Universal Socket 370 Intel 82801AA I/O Controller Hub component.
Page 15 Minimum voltage observed for a signal to extend below VSS at the device pad. Universal Socket 370 Refers to the Intel 815EG chipset using the “universal” PGA370 socket. In general, ® these designs support 66/100/133 MHz system bus operation, Intel ®...
Page 16: Reference Documents
Intel developer website ® Doc 290658 Intel 82802AB/82802AC Firmware Hub (FWH) Datasheet Intel developer website ® ® 82801BA I/O Controller Hub (ICH2) and Intel Doc 290687 Intel 82801BAM I/O Controller Hub (ICH2-M) Datasheet Intel developer website ® ® III Processor Specification Update (latest revision from website) http://developer.intel.co...
Page 17: System Overview
Introduction System Overview The 815EG chipset platform for use with the universal socket 370 contains a Graphics and Memory Controller Hub (GMCH) component and I/O Controller Hub 2 (ICH2) component for desktop platforms. The GMCH provides the processor interface (optimized for future 0.13 micron Celeron processors and Pentium III processors (socket 370) and the Pentium III processors (CPUID = 068xh), DRAM interface, hub interface, and internal graphics.
Page 18: System Features
1.4.1 System Features The 815EG chipset platform contains two components: the 82815EG Graphics and Memory Controller Hub (GMCH) and the 82801BA I/O Controller Hub 2 (ICH2). The GMCH integrates a 66/100/133 MHz, P6 family system bus controller, integrated 2D/3D graphics accelerator, 100/133 MHz SDRAM controller, and a high-speed accelerated hub architecture interface for communication with the ICH2.
Page 19: Component Features
 Support for x8, x16 DRAM device widths  Refresh mechanism: CAS-before-RAS only  Support for DIMM serial PD (presence detect) scheme via SMbus interface  Suspend-To-RAM (STR) power management support via self-refresh mode using CKE ® Intel 815EG Chipset Platform Design Guide...
Page 20: Intel ® 815 To 815G/Eg Signal Name Changes
Intel 82815G/EG pins associated with AGP signals have name changes. The following table shows the old Intel 82815 signal name, the ball number, and the new Intel 82815G/EG signal name. New designs for new 815G/EG boards should use pull-ups or pull-downs as indicated by the 815G/EG signal name.
Page 21: Intel ® 82801Ba I/O Controller Hub 2 (Ich2)
1.4.3.1 Universal Motherboard Design The 815EG chipset platform for use with the universal socket 370 allows systems designers to build one system that is compatible with the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors. When implemented, the 815EG chipset universal socket 370 platform can detect which processor is present in the socket and function accordingly.
Page 22: Intel ® Pc 133
1.4.3.6 Ultra ATA/100 Support The 815EG chipset platform incorporates an IDE controller with two sets of interface signals (primary and secondary) that can be independently enabled, tri-stated or driven low. The component supports Ultra ATA/100, Ultra ATA/66, Ultra ATA/33, and multiword PIO modes for transfers up to 100 MB/sec.
Page 23: Manageability And Other Enhancements
“AC- link.” The 815EG chipset platform’s AC ’97 (with the appropriate codecs) not only replaces ISA audio and modem functionality, but also improves overall platform integration by incorporating the AC- link.
Page 24 Wake-on-ring-from-suspend also is supported with the appropriate modem codec. The 815EG chipset platform expands audio capability with support for up to six channels of PCM audio output (i.e., full AC3 decode). Six-channel audio consists of Front Left, Front Right, Back Left, Back Right, Center and Woofer, for a complete surround sound effect.
Page 25: Figure 3. Ac '97 Audio And Modem Connections
AC’97 Modem Codec ® Intel ICH2 AC-link 360 EBGA AC’97 Audio Codec Audio Port c) AC'97 with Audio/Modem Codec Modem Port AC-link AC’97 ® Intel ICH2 Audio/ 360 EBGA Modem Codec Audio Port ® Intel 815EG Chipset Platform Design Guide...
Page 26: Low-Pin-Count (Lpc) Interface
1.4.3.10 Low-Pin-Count (LPC) Interface In the 815EG chipset platform, the Super I/O (SIO) component has migrated to the Low-Pin- Count (LPC) interface. Migration to the LPC interface allows for lower-cost Super I/O designs. The LPC Super I/O component requires the same feature set as traditional Super I/O components.
Page 27: General Design Considerations
Nominal Board Stack-Up The 815EG chipset platform requires a board stack-up yielding a target impedance of 60 Ω ± 15% with a 5-mil nominal trace width. Figure 4 shows an example stack-up that achieves this. It is a 4- layer printed circuit board (PCB) construction using 53%-resin FR4 material.
Page 28: Future Designs Require Pull-Ups And Pull-Downs On Any Unused Input And I/O Pins
Future Designs Require Pull-Ups and Pull-Downs on Any Unused Input and I/O Pins Any new 815EG platform Universal Socket 370 design should insure no input or I/O pin is left floating. For example, the TVCLKIN/INT# pin on many current 815 designs is left floating. This pin should be pulled up to 1.8 V by a weak pull-up resistor (8.2 kΩ...
Page 29: Figure 5. Top Signal Layer Before The Ground Fill Near The I/O Layer
4. Place stitching vias 100-150 mils apart in the entire ground fill Figure 5. Top Signal Layer before the Ground Fill Near the I/O Layer Figure 6. Top Signal Layer after the Ground Fill Near the I/O Layer Ground Fill ® Intel 815EG Chipset Platform Design Guide...
Page 30: Figure 7. Bottom Signal Layer Before The Ground Fill Near The I/O Area
General Design Considerations Figure 7. Bottom Signal Layer before the Ground Fill Near the I/O Area Figure 8. Bottom Signal Layer after the Ground Fill Near the I/O Ground Fill ® Intel 815EG Chipset Platform Design Guide...
Page 31: Component Layouts
Component Layouts Component Layouts Figure 9 illustrates the relative signal quadrant locations on the GMCH ballout. It does not represent the actual ballout. Refer to the Intel ® 82815 Chipset Family: 82815G/82815EG Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for the actual ballout.
Page 32: Figure 10. Ich2 360-Ball Ebga Quadrant Layout (Top View)
Component Layouts Figure 10 illustrates the relative signal quadrant locations on the ICH2 ballout. It does not represent the actual ballout. Refer to the Intel ® ® 82801BA I/O Controller Hub (ICH2) and Intel 82801BAM I/O Controller Hub (ICH2-M) Datasheet for the actual ballout.
Page 33: Figure 11. Firmware Hub (Fwh) Packages
Component Layouts Figure 11. Firmware Hub (FWH) Packages FWH Interface (32-Lead PLCC, FWH Interface 0.450" x 0.550") (40-Lead TSOP) Top View pck_fwh.vsd ® Intel 815EG Chipset Platform Design Guide...
Page 34 Component Layouts This page is intentionally left blank. ® Intel 815EG Chipset Platform Design Guide...
Page 35: Universal Socket 370 Design
Addition of resistor-divider network to provide 1.0 V, which will satisfy voltage tolerance requirements of ® the Pentium III processor ® (CPUID=068xh) and Celeron processor (CPUID=068xh) as well as future 0.13 micron socket 370 processors. ® Intel 815EG Chipset Platform Design Guide...
Page 36: Table 3. Gmch Considerations For Universal Socket 370 Design
The ICH2 must not The ICH2 will hold the GMCH in reset until initialize before the Intel CK-815 VTTPWRGD asserted plus 20 ms time clocks stabilize. delay to allow Intel CK-815 clocks to stabilize. ® Intel 815EG Chipset Platform Design Guide...
Page 37: Processor Design Requirements
Use of Universal Socket 370 Design with Incompatible GMCH The universal socket 370 design is intended for use with the 815EG chipset platform for use with the universal socket 370. A universal socket 370 design populated with an earlier stepping of the GMCH is not compatible with future 0.13 micron socket 370 processors and, if used, will cause...
Page 38: Identifying The Processor At The Socket
TUAL5# will be pulled to the 5 V rail. Figure 13. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit VCC5 VCC5 2.2 K Ω TUAL5 2.2 K Ω Ω MOSFET N Processor Pin AF36 TUAL5# Proc_Detect_815E_B0 ® Intel 815EG Chipset Platform Design Guide...
Page 39: Setting The Appropriate Processor Vtt Level
1.25 V or 1.5 V to VTT for AGTL or AGTL+, respectively. Figure 14. V Selection Switch VCC3_3 LT1587-ADJ Vout µ Ω 49.9 µ Tantalum µ M O SFET N Ω TUAL5 Vtt_Sel_Sw_815E_B0 ® Intel 815EG Chipset Platform Design Guide...
Page 40: Vtt Processor Pin Ag1
Figure 15. Switching Pin AG1 TUAL5 Processor Pin Note: The FET m ust have no m ore than 100 m illiohm s resistance between the source and the drain. Ω AG 1_Switch_815E_B0 ® Intel 815EG Chipset Platform Design Guide...
Page 41: Identifying The Processor At The Gmch
Table 6. Determining the Installed Processor via Hardware Mechanisms Processor Pin CPUPRES# Notes AF36 Hi-Z Future 0.13 micron socket 370 processor installed. ® Pentium III processor (CPUID=068xh) or ® Celeron processor (CPUID=068xh) installed. No processor installed. ® Intel 815EG Chipset Platform Design Guide...
Page 42: Configuring Non-Vtt Processor Pins
VTTPW RG D_Config_815E_B0 NOTES: The diode is included so that repeated pressing of the reset or power button does not cause the capacitor to build up enough charge to circumvent the 20 ms delay. ® Intel 815EG Chipset Platform Design Guide...
Page 43: Vcmos Reference
Referring to Figure 18, a network of resistors and a capacitor must be added so that this pin operates appropriately for whichever processor is in the socket. Figure 18. GTL_REF/VCMOS_REF Voltage Divider Network VCMO S Ω Processor Pin AK22 Ω µ GTL_CMOS_Ref_815E_B0 ® Intel 815EG Chipset Platform Design Guide...
Page 44: Processor Signal Pwrgood
See Figure 19 for an example implementation. Figure 19. Resistor Divider Network for Processor PWRGOOD VCC2_5 330 Ω PWRGOOD from PWRGOOD to Processor Power Connector and Reset Control Circuits 1.8 Κ Ω PWRGOOD_Divider_815E_B0 ® Intel 815EG Chipset Platform Design Guide...
Page 45: Apic Clock Voltage Switching Requirements
Figure 20 Voltage Switch for Processor APIC Clock IOAPIC Ω APICCLK_CPU Ω TUAL5 MOSFET N API_CLK_SW _815E_B0 NOTES: The 30 Ω resistor represents the series resistor typically used in connecting the APIC clock to the processor. ® Intel 815EG Chipset Platform Design Guide...
Page 46: Gtlref Topology And Layout
56 Ω pull-up to VTT. The resistor site should be located within 150 mils of the GMCH, and placed as close to the ADS# signal trace as possible. ® Intel 815EG Chipset Platform Design Guide...
Page 47: Power Sequencing On Wake Events
In addition to the mechanism for identifying the processor in the socket, special handling of wake events is required for the 815EG chipset platform that support functionality of the future 0.13 micron socket 370 processors. When a wake event is triggered, the GMCH and the CK-815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted.
Page 48: Ich2
PWROK to the ICH2, with the ICH2 subsequently taking the GMCH out of reset. Refer to Figure 23 for an example implementation. ® Figure 23 PWROK Gating Circuit for Intel ICH2 VDD on CK-815 VCC3_3...
Page 49: System Bus Design Guidelines
Grid Array 2 (FC-PGA2) package technology enables compatibility with previous Flip Chip-Pin Grid Array (FC-PGA) packages using the PGA370 socket. This section presents the considerations for designs capable of using the 815EG universal platform with the full range of Pentium III processors using the PGA370 socket.
Page 50: Table 7. Intel Pentium
Table 8 contains an example AGTL+ initial maximum flight time, and Table 9 contains an example minimum flight time calculation for a 133 MHz, uniprocessor system using the Pentium III processor and the 815EG chipset platform’s system bus. Note that assumed values were used for the clock skew and clock jitter.
Page 51: Flt_Min
0.15 NOTES: All times in nanoseconds The flight times in Table 8 include margin to account for the following phenomena that Intel observed when multiple bits are switching simultaneously. These multi-bit effects can adversely affect the flight time and signal quality and sometimes are not accounted for during simulation.
Page 52: General Topology And Layout Guidelines
5:10 or 6:12 Intergroup AGTL/AGTL+ signals (different group AGTL/AGTL+) 5:15 or 6:18 AGTL/AGTL+ to System Memory Signals 5:30 or 6:36 AGTL/AGTL+ to non-AGTL/AGTL+ 5:25 or 6:24 NOTES: Edge-to-edge spacing. Units are in mils. ® Intel 815EG Chipset Platform Design Guide...
Page 53: Motherboard Layout Rules For Agtl/Agtl+ Signals
5.2.1.3 Processor Connector Breakout It is strongly recommended that AGTL/AGTL+ signals do not traverse multiple signal layers. Intel recommends breaking out all signals from the connector on the same layer. If routing is tight, break out from the connector on the opposite routing layer over a ground reference and cross over to main signal layer near the processor connector.
Page 54: Minimizing Crosstalk
• Minimize the cross-sectional area of the traces. This can be done by means of narrower traces and/or by using thinner copper, but the trade-off for this smaller cross-sectional area is higher trace resistivity, which can reduce the falling-edge noise margin because of the I*R loss along the trace. ® Intel 815EG Chipset Platform Design Guide...
Page 55: Motherboard Layout Rules For Non-Agtl/Agtl+ (Cmos) Signals
5 mils 10 mils 1” to 9” STPCLK 5 mils 10 mils 1” to 9” THERMTRIP# 5 mils 10 mils 1” to 9” NOTES: Route these signals on any layer or combination of layers. ® Intel 815EG Chipset Platform Design Guide...
Page 56: Thrmdp And Thrmdn
VTT voltage should then be 1.25 V ± 3% for static conditions, and 1.25 V ± 9% for worst-case transient conditions. • Place resistor divider pairs for VREF generation at the GMCH component. VREF also is delivered to the processor. ® Intel 815EG Chipset Platform Design Guide...
Page 57: Electrical Differences For Universal Pga370 Designs
CPU_RST# must gate SW_ON# from ground. This prevents glitching on SW_ON# during power-up and power-down. The resistance to the base of the transistor gating CPU_RST# must be at least 2.2 k Ω for proper Vih levels on CPU_RST#. ® Intel 815EG Chipset Platform Design Guide...
Page 58: Thermtrip Timing
In addition, the example workaround circuits shown do not support production motherboard test methodologies that require the use of the processor JTAG/TAP port. Alternative workaround solutions must be found if such test capability is required. ® Intel 815EG Chipset Platform Design Guide...
Page 59: Pga370 Socket Definition Details
For Production Boards: Depopulate Resistor R5 To use ITP: Install Resistor R5, Depopulate Resistor R4 PGA370 Socket Definition Details Table 13 compares the pin names and functions of the Intel processors supported in the 815EG universal platform. Table 13. Processor Pin Definition Comparison...
Page 60 370 processors • Ground for Pentium III VTTPWRGD processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • VID control signal on future 0.13 micron socket 370 processors. • AGTL/AGTL+ termination AK16 Reserved voltage ® Intel 815EG Chipset Platform Design Guide...
Page 61 • AGTL termination voltage for future 0.13 micron socket 370 processors N37 2 • No connect for Pentium III NCHCTRL processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • NCHCTRL for future 0.13 micron socket 370 processors ® Intel 815EG Chipset Platform Design Guide...
Page 62: Bsel[1:0] Implementation Differences
BSEL[1:0] Implementation Differences A future 0.13 micron socket 370 processor will select the 133 MHz system bus frequency setting from the clock synthesizer. A Pentium III processor (CPUID=068xh) utilizes the BSEL1 pin to ® Intel 815EG Chipset Platform Design Guide...
Page 63: Clkref Circuit Implementation
VCC2.5 or VCC3.3 sources utilizing 1% tolerant resistors. A 4.7 µF decoupling capacitor should be included on this input. See Figure 30 and Table 14 for example CLKREF circuits. Do not use VTT as the source for this reference! ® Intel 815EG Chipset Platform Design Guide...
Page 64: Undershoot/Overshoot Requirements
There is also a time-dependent, non-linear overshoot and undershoot requirement that depends on the amplitude and duration of the overshoot/undershoot. See the appropriate processor datasheet for more details on the processor overshoot/undershoot specifications. ® Intel 815EG Chipset Platform Design Guide...
Page 65: Processor Reset Requirements
1 kΩ Chipset Pin X4 lenCS lenCPU Processor 22 Ω Pin AH4 10 pF sys_bus_reset_routin Table 15. RESET#/RESET2# Routing Guidelines (see Figure 31) Parameter Minimum (in) Maximum (in) LenCS LenITP LenCPU cs_rtt_stub cpu_rtt_stub ® Intel 815EG Chipset Platform Design Guide...
Page 66: Processor Pll Filter Recommendations
• < 0.5 dB attenuation in pass band (see DC drop in next set of requirements) • > 34 dB attenuation from 1 MHz to 66 MHz • > 28 dB attenuation from 66 MHz to core frequency The filter specification is graphically shown in Figure 32. ® Intel 815EG Chipset Platform Design Guide...
Page 67: Figure 32. Filter Specification
• DC voltage drop from VCC to PLL1 should be < 60 mV, which in practice implies series R < 2 Ω. This also means pass-band (from DC to 1 Hz) attenuation < 0.5 dB for VCC = 1.1 V, and < 0.35 dB for VCC = 1.5 V. ® Intel 815EG Chipset Platform Design Guide...
Page 68: Recommendation For Intel ® Platforms
System Bus Design Guidelines ® 5.9.3 Recommendation for Intel Platforms The following tables contains examples of components that meet Intel’s recommendations when configured in the topology of Figure 33. Table 16. Component Recommendations – Inductor Part Number Value Tolerance Rated...
Page 69: Figure 33. Example Pll Filter Using A Discrete Resistor
PLL1 Discrete resistor Processor PLL2 <0.1 Ω route PLL_filter_1 Figure 34. Example PLL Filter Using a Buried Resistor CORE <0.1 Ω route PLL1 T race resistance Processor PLL2 <0.1 Ω route PLL_filter_2 ® Intel 815EG Chipset Platform Design Guide...
Page 70: Custom Solutions
5.11 Decoupling Guidelines for Universal PGA370 Designs These preliminary decoupling guidelines for universal PGA370 designs are estimated to meet the specifications of Intel VRM guidelines for future 0.13 micron processors. 5.11.1 Decoupling Design CORE • Sixteen or more 4.7 µF capacitors in 1206 packages.
Page 71: Vtt Decoupling Design
• Twenty 0.1 µF capacitors in 0603 packages placed as closed as possible to the processor VTT pins. The capacitors are shown on the exterior of Figure 36. 5.11.3 VREF Decoupling Design • Four 0.1 µF capacitors in 0603 package placed near VREF pins (within 500 mils). ® Intel 815EG Chipset Platform Design Guide...
Page 72: Thermal Considerations
Note portions of the heatsink and attach hardware hang over the motherboard. Adhering to these keep-out areas will ensure compatibility with Intel boxed processor products and Intel enabled third-party vendor thermal solutions for high frequency processors. While the...
Page 73: Figure 37. Heatsink Volumetric Keep-Out Regions
System Bus Design Guidelines Figure 37. Heatsink Volumetric Keep-Out Regions Figure 38 Motherboard Component Keep-Out Regions ® Intel 815EG Chipset Platform Design Guide...
Page 74: Fan Heatsink Keep-Out Adherence For Future Boxed Intel Celeron Processors
Several previous 815 and 815E chipset based motherboards did not adhere to Intel specified keep- out requirements. When revising previous 815E motherboard designs to support the boxed Celeron processor manufactured on the 0.13-micron process technology, ensure motherboard...
Page 75: Debug Port Changes
(ITP) compatible with 1.5 V signal levels on the TAP. Previous ITPs were designed to work with higher voltages and may damage the processor if connected to any of these specified processors. See the processor datasheet for more information regarding the debug port. ® Intel 815EG Chipset Platform Design Guide...
Page 76 System Bus Design Guidelines This page is intentionally left blank. ® Intel 815EG Chipset Platform Design Guide...
Page 77: System Memory Design Guidelines
GMCH without a stitching capacitor as long as the trace on the topside of the PCB is less than 200 mils. Intel recommends that a parallel plate capacitor between VCC3.3SUS and GND be added to account for the current return path discontinuity (See Decoupling section). Use (1) .01uf X7R capacitor per every (5) system memory signals that switch plane references.
Page 78: System Memory 2-Dimm Design Guidelines
SCKE[3:2] Max. (64 Mbit) 256 MB SCSB[3:2]# Max. (128 Mbit) 512 MB SCSB[1:0]# SRAS# SCAS# SWE# 82815 SBS[1:0] SMAA[12:8,3:0] SMAA[7:4] SMAB[7:4]# SDQM[7:0] SMD[63:0] DIMM_CLK[3:0] CK815 DIMM_CLK[7:4] SMB_CLK SMB_DATA DIMM 0 & 1 sys_mem_conn_2DIMM ® Intel 815EG Chipset Platform Design Guide...
Page 79: System Memory 2-Dimm Layout Guidelines
SCAS#, SRAS#, SWE# SBS[1:0], SMAA[12:8,3:0] In addition to meeting the spacing requirements outlined in Table 19, system memory signal trace edges must be at least 30 mils from any other non-system memory signal trace edge. ® Intel 815EG Chipset Platform Design Guide...
Page 80: Figure 44. System Memory Routing Example
System Memory Design Guidelines Figure 44. System Memory Routing Example sys_mem_routing_ex NOTES: Routing in this figure is for example purposes only. It does not necessarily represent complete and correct routing for this interface. ® Intel 815EG Chipset Platform Design Guide...
Page 81: System Memory 3-Dimm Design Guidelines
Max. (128 Mbit) 512 MB SCKE[5:4] SCSB[5:4]# SCSB[3:2]# SCSB[1:0]# SRAS# SCAS# SWE# 82815 SBS[1:0] SMAA[12:8,3:0] SMAA[7:4] SMAB[7:4]# SMAC[7:4]# SDQM[7:0] SMD[63:0] DIMM_CLK[3:0] CK815 DIMM_CLK[7:4] DIMM_CLK[11:8] SMB_CLK SMB_DATA DIMM 0 & 1 & 2 sys_mem_conn_3DIMM ® Intel 815EG Chipset Platform Design Guide...
Page 82: System Memory 3-Dimm Layout Guidelines
Trace Lengths (inches) Width Spacing Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. SCS[5:4]# SCS[3:2]# SCS[1:0]# SMAA[7:4] SMAB[7:4]# SMAC[7:4} SCKE[5:4] SCKE[3:2] SCKE[1:0] SMD[63:0] 1.75 SDQM[7:0] SCAS#,SRAS#, SWE# SBS[1:0], SMAA[12:8,3:0] ® Intel 815EG Chipset Platform Design Guide...
Page 83: System Memory Decoupling Guidelines
(on layer 1 if the power plane is on layer 2 or on layer 4 if the power layer is on layer 3).     Figure 47. Intel 815 Chipset Platform Decoupling Example ® Intel 815EG Chipset Platform Design Guide...
Page 84: Figure 48. Intel ® 815 Chipset Decoupling Example
Capacitors should be placed between the DIMM connectors and evenly spread out across the SDRAM interface. For debug purposes, four or more 0603 capacitor sites should be placed on the backside of the board, evenly distributed under the 815EG chipset platform’s system memory interface signal field. ®...
Page 85: Compensation
A system memory compensation resistor (SRCOMP) is used by the GMCH to adjust the buffer ® characteristics to specific board and operating environment characteristics. Refer to the Intel Chipset Family: 82815G/82815EG Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for details on compensation.
Page 86 System Memory Design Guidelines This page is intentionally left blank. ® Intel 815EG Chipset Platform Design Guide...
Page 87: Display Cache Design Guidelines
Display Cache Design Guidelines Display Cache Interface The display cache interface of the 815EG chipset platform is similar to the 810E chipset. Note that the display cache is optional. There do not have to be any GPA (Graphics Performance Accelerator) card SDRAM devices connected to the interface. The only dedicated display cache signals are OCLK and RCLK, which need not connect directly to the SDRAM devices.
Page 88: Display Cache Clocking
VDDQ voltage must be maintained in 82815EG designs even though the AGP card capability is removed. For the designer developing an 82815EG motherboard, there is no distinction between VCC and VDDQ, as both are tied to the 3.3 V power plane on the motherboard. ® Intel 815EG Chipset Platform Design Guide...
Page 89: Integrated Graphics Display Output
The LC pi-filter consists of two 3.3 pF capacitors and a ferrite bead with a 75 Ω impedance at 100 MHz. The LC pi-filter is designed to filter glitches produced by the RAMDAC while maintaining adequate edge rates to support high-end display resolutions. ® Intel 815EG Chipset Platform Design Guide...
Page 90: Figure 50. Schematic Of Ramdac Video Interface
RAMDAC. An LC filter is recommended for connecting the segmented analog 1.85 V power plane of the RAMDAC to the 1.85 V board power plane. The LC filter should be designed for a cut-off frequency of 100 kHz. ® Intel 815EG Chipset Platform Design Guide...
Page 91: Reference Resistor (Rset) Calculation
Matching of the video routes (i.e., red, green, blue) from the RAMDAC to the VGA connector is also essential. The routing for these signals should be as similar as possible (i.e., same routing layer(s), same number of vias, same routing length, same bends, and jogs). ® Intel 815EG Chipset Platform Design Guide...
Page 92: Figure 52. Recommended Ramdac Component Placement And Routing
Via straight down to the ground plane RAMDAC_comp_placement_routing NOTES: Diodes D are clamping diodes with low leakage and low capacitive loading. An example is: California Micro Devices PAC DN006 (6 channel ESD protection array). ® Intel 815EG Chipset Platform Design Guide...
Page 93: Ramdac Layout Recommendations
HSYNC/VSYNC Output Guidelines The Hsync and Vsync output of the GMCH may exhibit up to 1.26 V P-P noise when driven high under high traffic system memory conditions. To minimize this, the following is required. ® Intel 815EG Chipset Platform Design Guide...
Page 94: Intel ® Digital Video Out
Leaving the Intel DVO Port Unconnected If the motherboard does not implement any of the possible video devices with the 815EG chipset universal platform’s DVO port, the following are recommended on the motherboard: • Pull up LTVDA and LTVCK with 4.7 kΩ resistors at the GMCH. This will prevent the GMCH’s DVO controller from confusing noise on these lines with false I...
Page 95 Integrated Graphics Display Output • Route LTVDATA[11:0] and LTVCLKOUT[1:0] out of the BGA to test points for use by automated test equipment (if required). These signals are part of one of the GMCH XOR chains. ® Intel 815EG Chipset Platform Design Guide...
Page 96 Integrated Graphics Display Output This page is intentionally left blank. ® Intel 815EG Chipset Platform Design Guide...
Page 97: Hub Interface
NAND Tree testing. Each signal should be routed such that it meets the guidelines documented for its signal group. Figure 54. Hub Interface Signal Routing Example NAND tree test point HL_STB HL11 HL_STB# ICH2 GMCH HL[10:0] GCLK CLK66 Clocks hub_link_sig_routing ® Intel 815EG Chipset Platform Design Guide...
Page 98: Data Signals
The reference voltage generated by a single HREF divider should be bypassed to ground at each component with a 0.01 µF capacitor located close to the component HREF pin. If the reference voltage is generated locally, the bypass capacitor must be close to the component HREF pin. ® Intel 815EG Chipset Platform Design Guide...
Page 99: Compensation
9.1.4 Compensation Independent hub interface compensation resistors are used by the GMCH and ICH2 to adjust buffer characteristics to specific board characteristics. Refer to the Intel ® 815 Chipset Family: 82815G/82815EG Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet and the Intel ®...
Page 100 Hub Interface This page is intentionally left blank. ® Intel 815EG Chipset Platform Design Guide...
Page 101: I/O Controller Hub 2 (Intel Ich2)
Refer to Figure 57 for a layout example, with the decoupling capacitors circled with an arrow showing which power plane/trace they are connected to. Intel recommends that, for prototype board designs, the designer include pads for extra power plane decoupling capacitors.
Page 102: Power Sequencing On Wake Events
I/O Controller Hub 2 (Intel® ICH2) ® Figure 57. Intel ICH2 Decoupling Capacitor Layout 3.3V Core 1.85V Core 1.85V Standby 3.3V Standby 1.85V Standby 3.3V Core 5V Ref decouple_cap_layo 10.2 Power Sequencing on Wake Events For systems providing functionality with future 0.13 micron socket 370 processors, special handling of wake events is required.
Page 103: Power Supply Ps_On Considerations
I/O Controller Hub 2 (Intel® ICH2) 10.3 Power Supply PS_ON Considerations • If a pulse on SLP_S3# or SLP_S5# is short enough (~ 10–100 mS) such that PS_ON is driven active during the exponential decay of the power rails, a few power supplies may not be designed to handle this short pulse condition.
Page 104 I/O Controller Hub 2 (Intel® ICH2) This page is intentionally left blank. ® Intel 815EG Chipset Platform Design Guide...
Page 105: O Subsystem
IDE channels. The ICH2 has integrated the series resistors that typically have been required on the IDE data signals (PDD[15:0] and SDD[15:0]) running to the two ATA connectors. Intel does not anticipate requiring additional series termination, but OEMs should verify the motherboard signal integrity via simulation.
Page 106: Combination Host-Side/Device-Side Cable Detection
IDE device. If a 40-conductor cable is detected, the system software must not enable modes faster than Ultra DMA Mode 2 (Ultra ATA/33). Intel recommends that cable detection be performed using a combination host-side/device-side detection mechanism. Note that host-side detection cannot be implemented on an NLX form factor system, since this configuration does not define interconnect pins for the PDIAG#/CBLID# from the riser (containing the ATA connectors) to the motherboard.
Page 107: Device-Side Cable Detection
The drive can detect the difference in rise times and will report the cable type to the BIOS when it sends the IDENTIFY_DEVICE packet during system boot, as described in the ATA/66 specification. ® Intel 815EG Chipset Platform Design Guide...
Page 108: Primary Ide Connector Requirements
The 10 k Ω resistor to ground on the PDIAG#/CBLID# signal is now required on the Primary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface. ® Intel 815EG Chipset Platform Design Guide...
Page 109: Secondary Ide Connector Requirements
The 10 k Ω resistor to ground on the PDIAG#/CBLID# signal is now required on the Primary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface. ® Intel 815EG Chipset Platform Design Guide...
Page 110: Figure 62. Intel ® Ich2 Ac '97- Codec Connection
Secondary codec ICH2_AC97_codec_conn Intel has developed an advanced common connector for both AC ’97 as well as networking options. This is known as the Communications and Network Riser (CNR). Refer to Section 11.3.1. The AC ’97 interface can be routed using 5 mil traces with 5 mil space between the traces.
Page 111: Communications Network Riser (Cnr)
CNR EEPROM can be accessed. The Figure 63 indicates the interface for the CNR connector. The Platform LAN Connection (PLC) can either be an Intel 82562EH or Intel 82562ET component. Refer to the CNR specification for additional information.
Page 112: Ac '97 Audio Codec Detect Circuit And Configuration Options
AC ’97 Audio Codec Detect Circuit and Configuration Options The following provides general circuits to implement a number of different codec configurations. For Intel recommended codec configurations, refer to the Intel ® White Paper Recommendations for ICHx/AC ’97 Audio (Motherboard and Communication and Network Riser).
Page 113: Figure 65. Cdc_Dn_Enab# Support Circuitry For Multi-Channel Audio Upgrade
Figure 66 shows the circuitry required on the motherboard to support a two-codec down configuration. This circuitry disables the codec on a single codec CNR. Notice that in this configuration the resistor, R , has been changed to 100 kΩ. ® Intel 815EG Chipset Platform Design Guide...
Page 114: Figure 66. Cdc_Dn_Enab# Support Circuitry For Two-Codecs On Motherboard / One-Codec On Cnr
The CDC_DN_ENAB# signal must be run to a GPI so that the BIOS can sense the state of the signal. CDC_DN_ENAB# is required to be connected to a GPI; a connection to a GPIO is strongly recommended for testing purposes. ® Intel 815EG Chipset Platform Design Guide...
Page 115: Valid Codec Configurations
It is therefore strongly recommended that the effective impedance be greater than 50 kΩ and the pull-down resistor be less than 7.3 kΩ. ® Intel 815EG Chipset Platform Design Guide...
Page 116: Ac '97 Routing
EMI emissions and degrading the analog and digital signal quality. • Analog power and signal traces should be routed over the analog ground plane. ® Intel 815EG Chipset Platform Design Guide...
Page 117: Motherboard Implementation
S5 state via the AC-link. • PC_BEEP should be routed through the audio codec. Care should be taken to avoid the introduction of a pop when powering the mixer up or down. ® Intel 815EG Chipset Platform Design Guide...
Page 118: Usb
The P+/P- signal traces must also be the same length. This will minimize the effect of common mode current on EMI. Lastly, do not route over plane splits. Figure 69 illustrates the recommended USB schematic. ® Intel 815EG Chipset Platform Design Guide...
Page 119: Disabling The Native Usb Interface Of Ich2
• On the processor:  PICCLK requires special implementation for universal motherboard designs.  Tie PICD0 to 2.5 V through 10 kΩ resistors.  Tie PICD1 to 2.5 V through 10 kΩ resistors. ® Intel 815EG Chipset Platform Design Guide...
Page 120: Pirq Routing Example
IRQs. It is up to the board designer to route these signals in a way that will prove the most efficient for their particular system. A PCI slot can be routed to share interrupts with any of the ICH2’s internal device/functions. ® Intel 815EG Chipset Platform Design Guide...
Page 121: Smbus/Smlink Interface
Intel does not support external access to the ICH2’s integrated LAN controller via the SMLink interface. Also, Intel does not support access to the ICH2’s SMBus slave interface by the ICH2’s SMBus host controller. Table 25 describes the pull-up requirements for different implementations of the SMBus and SMLink signals.
Page 122: Smbus Architecture And Design Considerations
If this SPD device needs to operate in STR, then it should be connected to the VCC_Suspend supply. • The ICH2 does not run SMBus cycles while in STR. • SMBus devices that can operate in STR must be powered by the VCC_Suspend supply. ® Intel 815EG Chipset Platform Design Guide...
Page 123: Figure 72. Unified Vcc_Suspend Architecture
In suspended modes where VCC is OFF and VCC_Suspend is on, the VCC node will be CORE CORE very near ground. In this case the input leakage of the ICH will be approximately 10 uA. ® Intel 815EG Chipset Platform Design Guide...
Page 124 5 V from those driving 3 V signal levels. • Devices that are powered by the VCC_Suspend well must not drive into other devices that are powered off. This is accomplished with the “bus switch”. ® Intel 815EG Chipset Platform Design Guide...
Page 125: Pci
The ICH2 supports six PCI Bus masters (excluding the ICH2), by providing six REQ#/GNT# pairs. In addition, the ICH2 supports two PC/PCI REQ#/GNT# pairs, one of which is multiplexed with a PCI REQ#/GNT# pair. Figure 75. PCI Bus Layout Example ICH2 IO_subsys_PCI_layout ® Intel 815EG Chipset Platform Design Guide...
Page 126: Rtc
RTCX1: Crystal input 1 – Connected to the 32.768 kHz crystal. VBIAS: RTC BIAS voltage – This pin is used to provide a reference voltage. This DC voltage sets a current that is mirrored throughout the oscillator and buffer circuitry. VSS: Ground ® Intel 815EG Chipset Platform Design Guide...
Page 127: External Capacitors
The voltage of the battery can affect the RTC accuracy. In general, when the battery voltage decays, the RTC accuracy also decreases. High accuracy can be obtained when the RTC voltage is within the range 3.0 V to 3.3 V. ® Intel 815EG Chipset Platform Design Guide...
Page 128: Figure 77. Diode Circuit To Connect Rtc External Battery
A standby power supply should be used in a desktop system, to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and, thereby, the RTC accuracy. ® Intel 815EG Chipset Platform Design Guide...
Page 129: Rtc External Rtcrst Circuit
INTRUDER# should have a weak external pull-up to VCCRTC. This will prevent these nodes from floating in G3, and correspondingly will prevent ICCRTC leakage that can cause excessive coin-cell drain. The PWROK input signal should also be configured with an external weak pull- down. ® Intel 815EG Chipset Platform Design Guide...
Page 130: Rtc Routing Guidelines
• Put a ground plane under all external RTC circuitry. • Do not route any switching signals under the external components (unless on the other side of the ground plane). ® Intel 815EG Chipset Platform Design Guide...
Page 131: Vbias Dc Voltage And Noise Measurements
1 Mb HomePNA* LAN 1 Mb HomePNA connection Intel developed a dual footprint for 82562ET and 82562EH, to minimize the required number of board builds. A single layout with the specified dual footprint allows the OEM to install the appropriate LAN connect component to satisfy market demand. Design guidelines are provided for each required interface and connection.
Page 132: Intel ® Ich2 - Lan Interconnect Guidelines
This interface supports both 82562EH and 82562ET/82562EM components. Both components share signal lines LAN_CLK, LAN_RSTSYNC, LAN_RXD[0], and LAN_TXD[0]. Signal lines LAN_RXD[2:1] and LAN_TXD[2:1] are not connected when 82562EH is installed. The AC characteristics for this interface are found in the Intel ® 82801BA I/O Controller Hub (ICH2) and ®...
Page 133: Bus Topologies
Signal lines LAN_RXD[2:1] and LAN_TXD[2:1] are not connected. Intel 82562ET 3.5” to 10” Intel 82562EM 4.5” to 8.5” 3” to 9” The trace length from the connector to LOM should be 0.5” to 3.0” ® Intel 815EG Chipset Platform Design Guide...
Page 134: Lom/Cnr Interconnect
• Stubs due to the resistor pack should not be present on the interface. • The resistor pack value can be 0 Ω or 22 Ω. • LAN on Motherboard PLC can be a dual-footprint configuration. ® Intel 815EG Chipset Platform Design Guide...
Page 135: Signal Routing And Layout
Motherboard impedances should be controlled to minimize the impact of any mismatch between the motherboard and the add-in card. An impedance of 60 Ω ± 15% is strongly recommended. Otherwise, signal integrity requirements may be violated. ® Intel 815EG Chipset Platform Design Guide...
Page 136: Line Termination
• Do not route traces and vias under crystals or oscillators. This will prevent coupling to or from the clock. And as a general rule, place traces from clocks and drives at a minimum distance from apertures, by a distance exceeding the largest aperture dimension. ® Intel 815EG Chipset Platform Design Guide...
Page 137: Figure 84. Trace Routing
• Separate and group signals by function on separate layers if possible. Maintain a gap of 100 mils between all differential pairs (Phoneline and Ethernet) and other nets, but group associated differential pairs together. ® Intel 815EG Chipset Platform Design Guide...
Page 138: Power And Ground Connections
• Route traces over a continuous plane with no interruptions (i.e., do not route over a split plane). If there are vacant areas on a ground or power plane, avoid routing signals over the vacant area. This will increase inductance and EMI radiation levels. ® Intel 815EG Chipset Platform Design Guide...
Page 139: A 4-Layer Board Design
Digital high-speed signals, which include all LAN interconnect interface signals, are routed on the bottom layer. 11.9.2.4 Common Physical Layout Issues Common physical layer design and layout mistakes in LAN On Motherboard designs are as follows: ® Intel 815EG Chipset Platform Design Guide...
Page 140 (Inferior magnetics modules often have less common-mode rejection and/or no auto- transformer in the transmit channel.) Another common mistake is using an Intel 82555 or Intel 82558 physical layer schematic in a PLC design. The transmit terminations and decoupling are different, and there also are differences in the receive circuit.
Page 141: Intel ® 82562Eh Home/Pna* Guidelines
As with most subsystems, the HomePNA LAN circuits must be as close as possible to the connector. Thus, it is imperative that all designs be optimized to fit in a very small space. ® Intel 815EG Chipset Platform Design Guide...
Page 142: Crystals And Oscillators
The transmit/receive differential signal pair is terminated with a pair of 51.1 Ω (1%) resistors. This parallel termination should be placed close to the Intel 82562EH. The center, common point between the 51.1 Ω resistors is connected to a voltage-divider network. The opposite end of one 806 Ω...
Page 143: Critical Dimensions
Asymmetrical and unequally long differential pairs contribute to common-mode noise. This can degrade the receive circuit performance and contribute to emissions radiated from the transmit side. ® Intel 815EG Chipset Platform Design Guide...
Page 144: Intel 82562Et / Intel 82562Em Guidelines
In addition, the 82562ET or 82562EM should be placed more than 1.5 inches away from any board edge to minimize the potential for EMI radiation problems. ® Intel 815EG Chipset Platform Design Guide...
Page 145: Crystals And Oscillators
‘A’ from the 82562ET or 82562EM to the magnetics module. The combined total distances A and B must not exceed 4 inches (preferably, less than 2 inches) (see Figure 89). ® Intel 815EG Chipset Platform Design Guide...
Page 146: Figure 89. Critical Dimensions For Component Placement
The measured trace impedance for layout designs targeting 100 Ω often result in lower actual impedance. OEMs should verify actual trace impedance and adjust their layouts accordingly. If the actual impedance is consistently low, a target of 105–110 Ω should compensate for second-order effects. ® Intel 815EG Chipset Platform Design Guide...
Page 147: Reducing Circuit Inductance
EFT (electrical fast transient) testing. If a discrete capacitor is used, it should be rated for at least 1000 Vac, to satisfy the EFT requirements. ® Intel 815EG Chipset Platform Design Guide...
Page 148: Intel ® 82562Et/82562Em Disable Guidelines
10 K Ω Lan_Disable2_815E_B0 There are 4 pins that are used to put the 82562ET controller in different operating states: Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. Table 31 describes the operational/disable features for this design. ® Intel 815EG Chipset Platform Design Guide...
Page 149: Intel ® 82562Et / Intel ® 82562Eh Dual Footprint Guidelines
Figure 92 and Figure 93. Figure 92. Dual-Footprint LAN Connect Interface LAN_CLK LAN_RSTSYNC 82562EH TQFP ICH2 LAN_RXD[2:0] LAN_TXD[2:0] Stub dual_ft_lan_conn Figure 93. Dual-Footprint Analog Interface 82562EH/82562ET 82562EH RJ11 Ring Config. Magnetics Module 82562ET RJ45 Config. dual_ft_AN_conn ® Intel 815EG Chipset Platform Design Guide...
Page 150: 815Eg Chipset Platform Design Guide
• Stub < 0.5 inch • Either 82562EH or 82562ET/82562EM can be installed, but not both. • Intel 82562ET pins 28,29, and 30 overlap with 82562EH pins 17,18, and 19. • Overlapping pins are tied to ground. • No other signal pads should overlap or touch.
Page 151: Lpc/Fwh
3.3 V plane to which the rest of the power pins are connected. This circuit also allows the board to operate with 3.3 V on this pin during normal operation. Figure 94. FWH VPP Isolation Circuitry 3.3V ® Intel 815EG Chipset Platform Design Guide...
Page 152: Fwh Decoupling
4.7 µF capacitor should be placed between the VCC supply pins and the VSS ground pin to decouple low frequency noise. The capacitors should be placed no further than 390 mils from the VCC supply pins. ® Intel 815EG Chipset Platform Design Guide...
Page 153: Clocking
Clocking Clocking For an 815EG universal platform, there are two clock specifications. One is for a 2-DIMM solution, and the other is for a 3-DIMM solution. In both specifications only single-ended clocking is supported. The 815EG Universal Socket 370 platforms using a future 0.13 micron socket 370 processor cannot implement differential clocking.
Page 154: Figure 95. Platform Clock Architecture For A 2-Dimm Solution
Clocking Figure 95 shows the 815EG chipset platform clock architecture for a 2-DIMM solution. Figure 95. Platform Clock Architecture for a 2-DIMM Solution Processor CPU 2_ITP APIC 0 2.5 V CPU 1 CPU 0 Clock Synthesizer Host unit PWRDWN# SEL1...
Page 155: 3-Dimm Clocking
• Three copies of 3 V, 66 MHz clock (3.3 V) • One copy of ref. clock at 14.31818 MHz (3.3 V) • Ref. 14.31818 MHz xtal oscillator input • Spread-spectrum support • I C support for turning off unused clocks ® Intel 815EG Chipset Platform Design Guide...
Page 156: Figure 96. Platform Clock Architecture For A 3-Dimm Solution
Clocking Figure 96 shows the 815EG chipset platform clock architecture for a 3-DIMM solution. Figure 96. Platform Clock Architecture for a 3-DIMM Solution Processor APIC 2.5 V CPU 1 CPU 0 CK 815 3D Host I/F 3V66 AGP local memory...
Page 157: Clock Routing Guidelines
CK815 Section 0 33 Ω GMCH Section 1 Section 3 CK815 Layout 4 33 Ω Section 1 Section 2 CK815 Layout 5 10 Ω Section 1 Section 2 CK815 Connector 22 pF clk_routing_topo ® Intel 815EG Chipset Platform Design Guide...
Page 158: Table 34. Simulated Clock Routing Solution Space
AC tuning. • Series resistor for clock guidelines: 22 Ω for GMCH SCLK and SDRAM clocks. All other clocks use 33 Ω. • Each DIMM clock should be matched within ±10 mils. ® Intel 815EG Chipset Platform Design Guide...
Page 159: Clock Driver Frequency Strapping
In addition to sampling BSEL[1:0] at reset, CK-815-compliant clock drivers are configured by the BIOS via a two-wire interface to drive SDRAM clock outputs at either 100 MHz (default) or 133 MHz (if all system requirements are met). ® Intel 815EG Chipset Platform Design Guide...
Page 160: Clock Skew Assumptions
1.0). • Motherboard clock routing must account for this additional electrical length. Therefore, AGPCLK routed to the connector must be shorter than HLCLK to the GMCH, to account for this additional 750 ps. ® Intel 815EG Chipset Platform Design Guide...
Page 161: Intel ® Ck-815 Power Gating On Wake Events
CK-815 is given sufficient time for the clocks to become stable. The amount of time required is a minimum 20 ms. ICH2 takes the GMCH out of reset. GMCH samples BSEL[1:0]. CK-815 will have sampled BSEL[1:0] much earlier. Refer to Section 4.3 for full implementation details. ® Intel 815EG Chipset Platform Design Guide...
Page 162 Clocking This page is intentionally left blank. ® Intel 815EG Chipset Platform Design Guide...
Page 163: Power Delivery
Note that the voltage on a dual power rail may be misleading. Figure 98 shows the power delivery architecture for an example system based on the 815EG platform. This power delivery architecture supports the “Instantly Available PC Design Guidelines”...
Page 164: Figure 98. Power Delivery Map
ICH2 and 815E to provide the separate voltages, a single regulator may be set to 1.795V - 1.910V. 6. ICH2 CMOS: The ICH2 pin is V_CPU_IO. Voltage depends on the CPU in use. ® Intel 815EG Chipset Platform Design Guide...
Page 165: 5V Dual Switch
Power Delivery In addition to the power planes provided by the ATX power supply, an instantly available 815EG universal platform (using Suspend-to-RAM) requires 6 power planes to be generated on the board. The requirements for each power plane are documented in this section. In addition to on-board voltage regulators, the CRB will have a 5V Dual Switch.
Page 166: 3.3Vsb
1.5 V plane used by VTT also provided VCMOS. Given that VTT can be either 1.25 V or 1.5 V in a universal socket 370 platform, it is necessary to provide VCMOS as its own separate plane. ® Intel 815EG Chipset Platform Design Guide...
Page 167: Thermal Design Power
= -t / (C * In(1-(V MIN / VCC MIN) ) ) Figure 99. Pull-Up Resistor Example m in. m ax. m ax m in m ax. m in. m ax. m ax. Leakage PW R_Pullup_R es_815E_B0 ® Intel 815EG Chipset Platform Design Guide...
Page 168: Atx Power Supply Pwrgood Requirements
• For an ATX power supply, when PSON is Low, the core wells are turned on. When PSON is high, the core wells from the power supply are turned off. ® Intel 815EG Chipset Platform Design Guide...
Page 169: Power Button Implementation
All lights, except a power state light, must be off. The system must be inaudible: silent or stopped fan, drives off. Contact Microsoft for the latest information concerning PC9x and Microsoft Logo programs. ® Intel 815EG Chipset Platform Design Guide...
Page 170: V/3.3 V Power Sequencing
ICH2’s RSMRST# and PWROK signals, since these signals control internal isolation logic between the various power planes: • RSMRST# controls isolation between the RTC well and the Resume wells. • PWROK controls isolation between the Resume wells and Main wells ® Intel 815EG Chipset Platform Design Guide...
Page 171: V5Ref/3.3 V Sequencing
VccSus3_3 rail. Otherwise when USB is supported, V5REF_SUS must be connected to 5V_AUX, which remains powered during S5. Figure 101. V5REF/3.3 V Sequencing Circuitry Vcc Supply (3.3 V) 5V Supply Ω µ To System VREF To System 3.3V_5V_Seq_Ckt_815E_B0 ® Intel 815EG Chipset Platform Design Guide...
Page 172: Power Plane Splits
Power Delivery 13.5 Power Plane Splits Figure 102. Power Plane Split Example pwr_plane_splits ® Intel 815EG Chipset Platform Design Guide...
Page 173: Glue Chip 3 (Ich2 Glue Chip)
13.6 Glue Chip 3 (ICH2 Glue Chip) To reduce the component count and BOM cost of the ICH2 platform, Intel has developed an ASIC component that integrates miscellaneous platform logic into a single chip. The Glue Chip 3 is designed to integrate some or all of the following functions into a single device. By integrating much of the required glue logic into a single device, overall board cost can be reduced.
Page 174 Power Delivery This page is intentionally left blank. ® Intel 815EG Chipset Platform Design Guide...
Page 175: System Design Checklist
This checklist highlights design considerations that should be reviewed prior to manufacturing a motherboard that implements an 815EG chipset platform for use with the universal socket 370 platform. This is not a complete list and does not guarantee that a design will function properly.
Page 176: Cmos Checklist
• 500-680 Ω pull-down resistor to ground / Connect to ITP. TRST# • Pull-up resistor that matches GTL characteristic impedance to VTT / 240 Ω PRDY# series resistor to ITP. Resistors need to be placed within 1inch of the TAP connector. ® Intel 815EG Chipset Platform Design Guide...
Page 177: Miscellaneous Checklist For 370-Pin Socket Processors
Optional override (jumpers, ASIC, etc.) could be used. May also connect to system monitoring device. • Pull up to VTT through 1 k Ω resistor and connect to VTTPWRGD circuitry. VTTPWRGD ® Intel 815EG Chipset Platform Design Guide...
Page 178: Gmch Checklist
• Connect 10 k Ω to ground. SMAA9 14.3.2 Hub Interface Checklist Checklist Items Recommendations • Connect to HUBREF generation circuitry. HUBREF • Pull up to VCC1.85 through 40 Ω (both GMCH and ICH2 side). HL_COMP ® Intel 815EG Chipset Platform Design Guide...
Page 179: Digital Video Output Port Checklist
• Tie the COMP pin to a 40 Ω 1% or 2% (or 39 Ω 1%) pull-up resistor (to HL_COMP VCC1.85) via a 10 mil wide, very short (~0.5 inch) trace. ZCOMP No longer supported. ® Intel 815EG Chipset Platform Design Guide...
Page 180: Lan Interface
Route Control Register. • In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. ® Intel 815EG Chipset Platform Design Guide...
Page 181  The APICCLK can either be tied to GND or connected to CK133, but not left floating.  Pull APICD[0:1] to GND through 10 k Ω pull-down resistors.  Use pull-downs for each APIC signal. Do not share resistor to pull signals ® Intel 815EG Chipset Platform Design Guide...
Page 182: Gpio Checklist
For more information, see the USB specification. • A fuse larger than 1A can be chosen to minimize the voltage drop. Fuse ® Intel 815EG Chipset Platform Design Guide...
Page 183: Power Management
• Connect to power monitoring logic, and should go high no sooner than 10 ms RSMRST# after both VCCSus3_3 and VCCSus1_8 have reached their nominal voltages. Requires weak pull-down. Also requires well isolation control as directed in Section 11.8.6. ® Intel 815EG Chipset Platform Design Guide...
Page 184: Processor Signals
• Ensure 10–20 ms RC delay (8.2 k Ω and 2.2 µ F). See Figure 76. RTCTST# • To assist in RTC circuit debug, route SUSCLK to a test point if it is unused. SUSCLK ® Intel 815EG Chipset Platform Design Guide...
Page 185: Figure 104. Intel ® Ich2 Oscillator Circuitry
• If the primary codec is down on the motherboard, this signal must be low to CDC_DN_ENAB# indicate the motherboard codec is active and controlling the AC ’97 interface. ® Intel 815EG Chipset Platform Design Guide...
Page 186: Miscellaneous Signals
Integrated Pull-Up 18-42 K Ω Stuff Jum per To Effective Im pedance Disable Tim eout Due To Speaker and Feature. Codec Circuit. Reff > 50 K Ω R < 7.3 K Ω Spkr_Ckt_815E_B0 ® Intel 815EG Chipset Platform Design Guide...
Page 187: Power
• VCMOS power source must supply 1.5 V and be generated by circuitry on the VCMOS motherboard. Do not connect to VTT. Figure 106. V5REF Circuitry Vcc Supply (3.3 V) 5V Supply Ω µ To System VREF To System 3.3V_5V_Seq_Ckt_815E_B0 ® Intel 815EG Chipset Platform Design Guide...
Page 188: Ide Checklist
 Connect a 0.047 µ F capacitor from IDE pin PDIAG/CBLID to GND. No ICH2 connection. Note that all ATA66/ATA100 drives will have the capability to detect cables The maximum trace length from the ICH2 to the ATA connector is 8 inches. ® Intel 815EG Chipset Platform Design Guide...
Page 189: Figure 107. Host/Device Side Detection Circuitry
10 k Ω 40-conductor cable PDIAG# ICH2 PDIAG# PDIAG#/ CBLID# 0.047 µF IDE drive IDE drive 10 k Ω 10 k Ω 80-conductor IDE cable PDIAG# PDIAG# ICH2 PDIAG#/ CBLID# 0.047 µF Open IDE_dev_cable_det ® Intel 815EG Chipset Platform Design Guide...
Page 190: Lpc Checklist
RI#1, CTS#0, RXD1, RXD0, RI#0, DCD#1, DSR#1, DSR#0, DTR#1, DTR#0, DCD#0, RTS#1, RTS#0, CTS#1, TXD1, TXD0 SERIRQ Pull up through 8.2 kΩ resistor to VCC3_3. LFRAME# No required pull-up resistor LDRQ#0 No required pull-up resistor ® Intel 815EG Chipset Platform Design Guide...
Page 191: System Checklist
• FWH RST# must be connected to PCIRST#. RST# • For a system with only one FWH device, tie ID[3:0] to ground. ID[3:0] ® These recommendations are only valid for the Intel Firmware Hub. ® Intel 815EG Chipset Platform Design Guide...
Page 192: Clock Synthesizer Checklist
Pass through 10 Ω resistor. MEMCLK1/DRAM_1, MEMCLK2/DRAM_2, MEMCLK3/DRAM_3, MEMCLK4/DRAM_4, MEMCLK5/DRAM_5, MEMCLK6/DRAM_6, MEMCLK7/DRAM_7 SCLK Pass through 22 Ω resistor. VCC3.3 Connected to VTTPWRGD gating circuit according to information in Section 4.3.1 for systems supporting the universal PGA370 design. ® Intel 815EG Chipset Platform Design Guide...
Page 193: System Memory Checklist
CKE[5…0] (For 3-DIMM GMCH are used. (0,1 for DIMM0; 2, 3 for DIMM1; 4,5 for DIMM2) implementation) • Connect to GND (since this 815EG chipset platform does not support REGE registered DIMMs). • Add a 4.7 k Ω pull-up resistor to 3.3 V. This recommendation write-protects WP (Pin 81 on the the DIMMs EEPROM.
Page 194 System Design Checklist This page is intentionally left blank. ® Intel 815EG Chipset Platform Design Guide...
Page 195: Third-Party Vendor Information
815EG chipset platform. The list of vendors can be used as a starting point for the designer. Intel does not endorse any one vendor, nor guarantee the availability or functionality of outside components. Contact the manufacturer for specific information regarding performance, availability, pricing and compatibility.
Page 196 Texas Instrument Greg Davis[gdavis@ti.com] (214) 480-3662 Combo TMDS Transmitters/TV Encoders Chrontel Chi Tai Hong [cthong@chrontel.com] (408) 544-2150 Texas Instrument Greg Davis[gdavis@ti.com] (214) 480-3662 LVDS Transmitter National Semiconductor 387R Jason Lu [Jason.Lu@nsc.com] (408) 721-7540 ® Intel 815EG Chipset Platform Design Guide...

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