Power Sequencing On Wake Events; Gating Of Intel ® Ck-815 To Vttpwrgd; Figure 22. Gating Power To Intel ® Ck-815 - Intel 815EG Design Manual

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4.3

Power Sequencing on Wake Events

In addition to the mechanism for identifying the processor in the socket, special handling of wake
events is required for the 815EG chipset platform that support functionality of the future 0.13
micron socket 370 processors. When a wake event is triggered, the GMCH and the CK-815 must
not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by setting up the
following sequence of events:
1. Power is not connected to the CK-815-compliant clock driver until VTTPWRGD12 is
asserted.
2. Clocks to the ICH2 stabilize before the power supply asserts PWROK to the ICH2. There is
no guarantee this will occur as the implementation for the previous step relies on the 12V
supply. Thus it is necessary to gate PWROK to the ICH2 from the power supply while the
CK-815 is given sufficient time for the clocks to become stable. The amount of time required
is a minimum 20 ms.
3. ICH2 takes the GMCH out of reset.
4. GMCH samples BSEL[1:0]. CK-815 will have sampled BSEL[1:0] much earlier.
4.3.1 Gating of Intel
System designers must ensure that the VTTPWRGD signal is asserted before the CK-815-
compliant clock driver receives power. This is handled by having the 3.3 V rail of the clock driver
gated by the VTTPWRGD12 reference schematic signal. Unlike previous 815EG chipset designs,
the 3.3 V standby rail is not used to power the clock because the VTTPWRGD12 reference
schematic signal will cut power to the clock when going into any sleep state. Refer to Figure 22 for
an example implementation.
Figure 22. Gating Power to Intel
®
Intel 815EG Chipset Platform Design Guide
®
CK-815 to VTTPWRGD
®
CK-815
MO SFET N
VTT PW RGD12
Note: The FET m ust have no m ore than
100 m illiohm s resistance between the
source and the drain.
Universal Socket 370 Design
VCC3_3
VDD on CK-815
47