Clock Skew Assumptions; Table 35. Simulated Clock Skew Assumptions - Intel 815EG Design Manual

Clocking
12.5

Clock Skew Assumptions

The clock skew assumptions in are used in the system clock simulations.

Table 35. Simulated Clock Skew Assumptions

HCLK @ GMCH to HCLK @ processor
HCLK @ GMCH to SCLK @ GMCH
SCLK @ GMCH to SCLK @ SDRAM
HLCLK @ GMCH to SCLK @ GMCH
HLCLK @ GMCH to HCLK @ GMCH
HLCLK @ GMCH to HLCLK @ ICH
HLCLK @ ICH to PCICLK @ ICH
PCICLK @ ICH to PCICLK @ other PCI
devices
HLCLK @ GMCH to AGPCLK @ connector
160
Skew Relationships Target Tolerance (±)
0 ns 150 ps
0 ns 600 ps
0 ns 630 ps
0 ns 900 ps
0 ns 700 ps
0 ns 375 ps
0 ns 900 ps
0 ns 2.0-ns window
®
Intel 815EG Chipset Platform Design Guide
Notes
Assumes ganged clock
outputs will allow max of
50 ps skew
500 ps pin-to-pin skew
100 ps board/package skew
250 ps pin-to-pin skew
380 ps board + DIMM
variation
• 500 ps pin-to-pin skew
• 400 ps board/package
skew
• 500 ps pin-to-pin skew
• 200 ps board/package
skew
• 175 ps pin-to-pin skew
• 200 ps board/package
skew
• 500ps pin-to-pin skew
• 400 ps board/package
skew
• 500 ps pin-to-pin skew
• 1.5 ns board/add-in skew
• Total electrical length of
AGP connector + add-in
card is 750 ps (according
to AGP2.0 spec and AGP
design guide 1.0).
• Motherboard clock routing
must account for this
additional electrical
length. Therefore,
AGPCLK routed to the
connector must be
shorter than HLCLK to
the GMCH, to account for
this additional 750 ps.
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