Intel 815EG Design Manual page 4

4.3 Power Sequencing on Wake Events ....................................................................47
4.3.1
4.3.2
5 System Bus Design Guidelines .........................................................................................49
5.1 System Bus Routing Guidelines ...........................................................................49
5.1.1
5.2 General Topology and Layout Guidelines.............................................................52
5.2.1
5.2.2
5.2.3
5.2.4
5.3 Electrical Differences for Universal PGA370 Designs ..........................................57
5.3.1
5.4 PGA370 Socket Definition Details ........................................................................59
5.5 BSEL[1:0] Implementation Differences.................................................................62
5.6 CLKREF Circuit Implementation ...........................................................................63
5.7 Undershoot/Overshoot Requirements ..................................................................64
5.8 Processor Reset Requirements............................................................................65
5.9 Processor PLL Filter Recommendations ..............................................................66
5.9.1
5.9.2
5.9.3
5.9.4
5.10 Voltage Regulation Guidelines..............................................................................70
5.11 Decoupling Guidelines for Universal PGA370 Designs ........................................70
5.11.1
5.11.2
5.11.3
5.12 Thermal Considerations........................................................................................72
5.12.1
5.12.2
5.13 Debug Port Changes ............................................................................................75
6 System Memory Design Guidelines...................................................................................77
6.1 System Memory Routing Guidelines.....................................................................77
6.2 System Memory 2-DIMM Design Guidelines ........................................................78
6.2.1
6.2.2
6.3 System Memory 3-DIMM Design Guidelines ........................................................81
6.3.1
6.3.2
6.4 System Memory Decoupling Guidelines ...............................................................83
4
®
Gating of Intel CK-815 to VTTPWRGD ...............................................47
Gating of PWROK to Intel
Initial Timing Analysis ............................................................................49
Motherboard Layout Rules for AGTL/AGTL+ Signals ...........................53
5.2.1.1 Ground Reference ...............................................................53
5.2.1.2 Reference Plane Splits ........................................................53
5.2.1.3 Processor Connector Breakout............................................53
5.2.1.4 Minimizing Crosstalk ............................................................54
Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals .....55
THRMDP and THRMDN .......................................................................56
Additional Routing and Placement Considerations ...............................56
THERMTRIP Circuit ..............................................................................57
5.3.1.1 THERMTRIP Timing ............................................................58
5.3.1.2 THERMTRIP Support for 0.13 Micron Technology
Processors, A-1 Stepping ....................................................58
Topology................................................................................................66
Filter Specification .................................................................................66
Recommendation for Intel
Custom Solutions ..................................................................................70
VCC Decoupling Design .................................................................70
CORE
VTT Decoupling Design ........................................................................71
VREF Decoupling Design......................................................................71
Heatsink Volumetric Keep-Out Regions................................................72
Fan Heatsink Keep-Out Adherence for Future Boxed Intel
Processors ............................................................................................74
System Memory 2-DIMM Connectivity ..................................................78
System Memory 2-DIMM Layout Guidelines .........................................79
System Memory 3-DIMM Connectivity ..................................................81
System Memory 3-DIMM Layout Guidelines .........................................82
®
ICH2 ..........................................................48
®
Platforms ...................................................68
®
Intel 815EG Chipset Platform Design Guide
R
® ®
Celeron