Thermtrip Timing; Thermtrip Support For 0.13 Micron Technology Processors, A-1 Stepping - Intel 815EG Design Manual

System Bus Design Guidelines
5.3.1.1

THERMTRIP Timing

When the THERMTRIP signal is asserted, both the VCC and VTT supplies to the processor must
be turned off to prevent thermal runaway of the processor. The time required from THERMTRIP
asserted to VCC rail at ½ nominal is 5 s, and THERMTRIP asserted to VTT rail at ½ nominal is
5 s. System designers must ensure that the decoupling scheme used on these rails does not violate
the THERMTRIP timing specifications.
5.3.1.2 THERMTRIP Support for 0.13 Micron Technology Processors, A-1
Stepping
A platform supporting the 0.13 micron technology processor must implement a workaround
required for the A-1 stepping of that processor, identified by CPUID = 6B1h.
The internal control register bit responsible for operation of the THERMTRIP circuit functionality
may power up in an un-initialized state. As a result, THERMTRIP# may be incorrectly asserted
during de-assertion of RESET# at nominal operating temperatures. When THERMTRIP# is
asserted as a result of this, the processor may shut down internally and stop execution. In addition,
when the THERMTRIP# pin is asserted the processor may incorrectly continue to execute, leading
to intermittent system power-on boot failures. The occurrence and repeatability of failures is
system dependent, however all systems and processors are susceptible to failure.
To prevent the risk of power-on boot failures, a platform workaround is required. The system must
provide a rising edge on the TCK signal during the power-on sequence that meets all of the
following requirements:
• •Rising edge occurs after VCC_CORE is valid and stable
• •Rising edge occurs before or at the de-assertion of RESET#
• •Rising edge occurs after all VREF input signals are at valid voltage levels
• •TCK input meets the VIH min (1.3 V) and max (1.65 V) spec requirements
Specific workaround implementations may be platform specific. The following examples have
been tested as acceptable workaround implementations.
Note: The example workaround circuits attached require circuit modification for ITP tools to
function correctly. These modifications must remove the workaround circuitry from the platform
and may cause systems to fail to boot. Review the accompanying notes with each workaround for
ITP modification details. If the system fails to boot when using ITP, issuing the ITP 'Reset Target'
command on failing systems will reset the system and provide a sufficient rising edge on the TCK
pin to ensure proper system boot.
In addition, the example workaround circuits shown do not support production motherboard test
methodologies that require the use of the processor JTAG/TAP port. Alternative workaround
solutions must be found if such test capability is required.
58
®
Intel 815EG Chipset Platform Design Guide
R