Electrical Differences For Universal Pga370 Designs; Thermtrip Circuit; Figure 27. Example Implementation Of Thermtrip Circuit - Intel 815EG Design Manual

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5.3 Electrical Differences for Universal PGA370
Designs
There are several electrical changes between previous PGA370 designs and the universal PGA370
design, as follows:
• Changes to the PGA370 socket pin definitions.
• Addition of VTTPWRGD signal to ensure stable VID selection for future 0.13 micron socket
370 processors.
• Addition of THERMTRIP circuit to allow processor to detect catastrophic overheat.
• Addition of VID[25mV] signal to support future 0.13 micron socket 370 processors.
• Processor VTT level is switchable to 1.25 V or 1.5 V, depending on which processor is
present in the socket.
• In designs using future 0.13 micron socket 370 processors, the processor does not generate
V
CMOS
5.3.1

THERMTRIP Circuit

To ensure that the processor detects and prevents catastrophic overheat, THERMTRIP is required
on all designs that support future 0.13 micron socket 370 processors. Figure 27 offers one possible
implementation that makes use of the 4s Power Button feature on the ICH2.

Figure 27. Example Implementation of THERMTRIP Circuit

Therm trip#
NOTES:
1.
2.
3.
4.
5.
®
Intel 815EG Chipset Platform Design Guide
_REF.
1.5V
4.7 K Ω
1 K Ω
CPU_RST#
The pull-up voltage on the collector of Q1 is required to be 1.8 V derived from a 3.3 V source.
THERMTRIP is not valid until after CPU_RST# is deasserted. This is handled by gating the
assertion of THERMTRIP with CPU_RST#. Using the CPU_RST# in this manner has minimal
impact to the signal quality.
THERMTRIP must not go higher than VccCMOS levels. The pull-up on THERMTRIP is now
connected to 1.5 V.
CPU_RST# must gate SW_ON# from ground. This prevents glitching on SW_ON# during power-up
and power-down.
The resistance to the base of the transistor gating CPU_RST# must be at least 2.2 k Ω for proper
Vih levels on CPU_RST#.
1.8V
1 K Ω
1 K Ω
Q1
2.2 K Ω
System Bus Design Guidelines
SW _ON#
Q2
Q3
Thermstrip_2
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