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System Design Checklist
Checklist Items
VREF[6:0]
VTT
NO CONNECTS
AJ3
EDGCTRL (AG1)
DETECT (AF36)
NCHCTRL (N37)
14.3
GMCH Checklist
14.3.1
System Memory Interface Checklist
Checklist Items
SMAA12
SMAA9
14.3.2
Hub Interface Checklist
Checklist Items
HUBREF
HL_COMP
178
• Connect to VREF voltage divider made up of 75 Ω and 150 Ω 1% resistors
connected to VTT. Processor VREF must be able to be separate from chipset
VREF.
• Decoupling Guidelines:
• 4 ea. (min.) 0.1 µ F in 0603 package placed within 500 mils of VREF pins
• Connect AH20, AK16, AL13, AL21, AN11, AN15, G35, G37, AD36, AB36,
X34, AA33, AA35, AN21, E23, S33, S37, U35, and U37 to VRM regulators
compliant with VRM guidelines for future 0.13 micron processors. Provide
high- and low-frequency decoupling.
• Decoupling Guidelines:
• 20 ea (min.) 0.1 µ F in 0603 package placed as near the VTT processor pins
as possible.
• 4 ea (min.) 0.47 µ F in 0612 package
• The following pins must be left as no-connects: A29, A31, A33, AC37, AK24,
AK30, AL1, AL11, AM2, AN13, AN23, B36, C29, C31, C33, C35, E21, E29,
E31, E35, E37, F10, G33, L33, N33, N35, Q33, Q35, Q37, R2, V4, W35, X2,
Y1, Z36.
• See Chapter 4.
• See Section 4.2.4
• See Section 4.2.2.
• 14 Ω pull-up resistor to VTT.
• Connect GMCH through 10 k Ω resistor to transistor junction as per
Chapter 4 for systems supporting the universal PGA370 design.
• Connect 10 k Ω to ground.
• Connect to HUBREF generation circuitry.
• Pull up to VCC1.85 through 40 Ω (both GMCH and ICH2 side).
Intel
Recommendations
Recommendations
Recommendations
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815EG Chipset Platform Design Guide
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