Intel 815EG Design Manual page 11

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Figure 102. Power Plane Split Example ..........................................................................172
Figure 103. USB Data Line Schematic ............................................................................183
Figure 104. Intel
Figure 105. SPKR Circuitry..............................................................................................186
Figure 106. V5REF Circuitry............................................................................................187
Figure 107. Host/Device Side Detection Circuitry............................................................189
Figure 108. Device Side Only Cable Detection ...............................................................189
Tables
Table 1. Intel
Table 2. Processor Considerations for Universal Socket 370 Design...............................35
Table 3. GMCH Considerations for Universal Socket 370 Design ....................................36
Table 4. Intel
Table 5. Clock Synthesizer Considerations for Universal Socket 370 Design ..................37
Table 6. Determining the Installed Processor via Hardware Mechanisms ........................41
Table 7. Intel
Calculations ................................................................................................................50
Table 8. Example T
Table 9. Example T
Table 10. Trace Guidelines for Figure 24 ..........................................................................52
Table 11. Trace Width: Space Guidelines.........................................................................52
Table 12. Routing Guidelines for Non-AGTL/AGTL+ Signals ...........................................55
Table 13. Processor Pin Definition Comparison................................................................59
Table 14. Resistor Values for CLKREF Divider (3.3 V Source).........................................64
Table 15. RESET#/RESET2# Routing Guidelines (see Figure 31)...................................65
Table 16. Component Recommendations - Inductor........................................................68
Table 17. Component Recommendations - Capacitor .....................................................68
Table 18. Component Recommendation - Resistor .........................................................68
Table 19. System Memory 2-DIMM Solution Space..........................................................79
Table 20. System Memory 3-DIMM Solution Space..........................................................82
Table 21. Decoupling Capacitor Recommendation .........................................................101
Table 22. Signal Descriptions ..........................................................................................115
Table 23. Codec Configurations ......................................................................................115
Table 24. IOAPIC Interrupt Inputs 16 thru 23 Usage.......................................................120
Table 25. Pull-Up Requirements for SMBus and SMLink................................................122
Table 26. LAN Connect ...................................................................................................131
Table 27. Single-Solution Interconnect Length Requirements (See Figure 81) ..............133
Table 28. LOM/CNR Length Requirements (See Figure 82)...........................................134
Table 29. Critical Dimensions for Component Placement (Refer to Figure 87) ..............143
Table 30. Critical Dimensions for Component Placement (see Figure 89) .....................146
Table 31. Intel
Table 32. Intel
Table 33. Intel
Table 34. Simulated Clock Routing Solution Space ........................................................158
Table 35. Simulated Clock Skew Assumptions ...............................................................160
Table 36. Power Delivery Definitions ...............................................................................163
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Intel 815EG Chipset Platform Design Guide
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ICH2 Oscillator Circuitry......................................................................185
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82815 to Intel 82815G Pin Name Changes..............................................20
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ICH2 Considerations for Universal Socket 370 Design .............................36
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Pentium III Processor AGTL/AGTL+ Parameters for Example
Calculations for 133 MHz Bus ................................................51
FLT_MAX
Calculations (Frequency Independent) ....................................51
FLT_MIN
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82562ET Operating States.....................................................................149
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CK-815 (2-DIMM) Clocks.......................................................................153
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CK-815 (3-DIMM) Clocks.......................................................................155
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