General Design Considerations; Nominal Board Stack-Up; Figure 4. Board Construction Example For 60 Ω Nominal Stack-Up - Intel 815EG Design Manual

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General Design Considerations

This design guide provides motherboard layout and routing guidelines for systems based on the
815EG chipset for use with the universal socket 370. The document does not discuss the functional
aspects of any bus or the layout guidelines for an add-in device.
If the guidelines listed in this document are not followed, it is very important that thorough signal
integrity and timing simulations be completed for each design. Even when the guidelines are
followed, critical signals should be simulated to ensure the proper signal integrity and flight time.
As bus speeds increase, it is imperative that the guidelines documented are followed precisely.
Any deviation from these guidelines should be simulated.
The trace impedance typically noted (i.e., 60 Ω ± 15%) is the "nominal" trace impedance for a
5 mil-wide trace. That is, it is the impedance of the trace when not subjected to the fields created
by changing current in neighboring traces. When calculating flight times, it is important to
consider the minimum and maximum impedance of a trace, based on the switching of neighboring
traces. The use of wider spaces between the traces can minimize this trace-to-trace coupling. In
addition, these wider spaces reduce crosstalk and settling time.
Coupling between two traces is a function of the coupled length, the distance separating the traces,
the signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects
of trace-to-trace coupling, follow the routing guidelines documented in this section.
The routing guidelines in this design guide have been created using a PCB stack-up similar to that
shown in Figure 4. If this stack-up is not used, extremely thorough simulations of every interface
must be completed. Using a thicker dielectric (prepreg) will make routing very difficult or
impossible.
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Nominal Board Stack-Up

The 815EG chipset platform requires a board stack-up yielding a target impedance of 60 Ω ± 15%
with a 5-mil nominal trace width. Figure 4 shows an example stack-up that achieves this. It is a 4-
layer printed circuit board (PCB) construction using 53%-resin FR4 material.
Figure 4. Board Construction Example for 60 Ω Ω Ω Ω Nominal Stack-up
®
Intel 815EG Chipset Platform Design Guide
Component-side layer 1: ½ oz. Cu
4.5-mil prepreg
Power plane layer 2: 1 oz. Cu
~48-mil core
Ground layer 3: 1 oz. Cu
4.5-mil prepreg
Solder-side layer 4: ½ oz. Cu
General Design Considerations
Total thickness:
62 mils
board_4.5mil_stackup
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