Power; Figure 106. V5Ref Circuitry - Intel 815EG Design Manual

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14.4.15

Power

Checklist Items
V_CPU_IO[1:0]
VCCRTC
VCC3.3
VCCSus3.3
VCC1.85
VCCSus1.85
V5_REF SUS
5V_REF
VCMOS

Figure 106. V5REF Circuitry

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Intel 815EG Chipset Platform Design Guide
• The power pins should be connected to the proper power plane for the
processor's CMOS Compatibility Signals. Use one 0.1 µ F decoupling capacitor.
• No clear CMOS jumper on VCCRTC. Use a jumper on RTCRST# or a GPI, or
use a safemode strapping for Clear CMOS
• Requires six 0.1 µ F decoupling capacitor
• Requires one 0.1 µ F decoupling capacitor.
• Requires two 0.1 µ F decoupling capacitor s.
• Requires one 0.1 µ F decoupling capacitor.
• Requires one 0.1 µ F decoupling capacitor.
• V5REF_SUS affects 5V-tolerance for all USB pins and can be connected to
VccSUS3_3 if ICH2 USB is not supported in the platform. If USB is supported,
5VREF_SUS must be connected to 5V_AUX, which remains powered during
S5.
• 5VREF is the reference voltage for 5 V tolerant inputs in the ICH2. Tie to pins
VREF[2:1]. 5VREF must power up before or simultaneous to VCC3_3. It must
power down after or simultaneous to VCC3_3. Refer to Figure 106 for an
example circuit schematic that may be used to ensure the proper 5VREF
sequencing.
• VCMOS power source must supply 1.5 V and be generated by circuitry on the
motherboard. Do not connect to VTT.
Vcc Supply
(3.3 V)
To System VREF
System Design Checklist
Recommendations
5V Supply
1 K Ω
1 µ F
To System
3.3V_5V_Seq_Ckt_815E_B0
187