Usb; Using Native Usb Interface - Intel 815EG Design Manual

I/O Subsystem
11.4

USB

11.4.1

Using Native USB Interface

The general guidelines for the USB interface are as follows:
• Unused USB ports should be terminated with 15 kΩ pull-down resistors on both P+/P- data
lines.
• 15 Ω series resistors should be placed as close as possible to the ICH2 (<1 inch). These series
resistors are required for source termination of the reflected signal.
• An optional capacitor (0pF - 47pF) cap may be placed as close as possible to the USB
connector side of the series resistors on the USB data lines (P0+/-, P1+/-, P2+/-, P3+/-). This
capacitor should be sized to minimize EMI radiation while still maintaining signal quality
(rise/fall time, Vcrs, etc.).
• 15 kΩ ± 5% pull-down resistors should be placed on the USB side of the series resistors on
the USB data lines (P0± ... P3±), and they are REQUIRED for signal termination by the
USB specification. The stub should be as short as possible.
• The trace impedance for the P0±...P3± signals should be 45 Ω (to ground) for each USB
signal P+ or P-. When the stack-up recommended in Section 2.1 is used, the USB requires
9-mil traces. The impedance is 90 Ω between the differential signal pairs P+ and P-, to match
the 90 Ω USB twisted-pair cable impedance. Note that the twisted-pair's characteristic
impedance of 90 Ω is the series impedance of both wires, resulting in an individual wire
presenting a 45 Ω impedance. The trace impedance can be controlled by carefully selecting
the trace width, trace distance from power or ground planes, and physical proximity of nearby
traces.
• USB data lines must be routed as critical signals. The P+/P- signal pair must be routed
together, parallel to each other on the same layer, and not parallel with other non-USB signal
traces to minimize crosstalk. Doubling the space from the P+/P- signal pair to adjacent signal
traces will help to prevent crosstalk. Do not worry about crosstalk between the two P+/P-
signal traces. The P+/P- signal traces must also be the same length. This will minimize the
effect of common mode current on EMI. Lastly, do not route over plane splits.
Figure 69 illustrates the recommended USB schematic.
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Intel 815EG Chipset Platform Design Guide
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