Intel 82563EB Design Manual
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Intel 82563EB Design Manual

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82563EB/82564EB LAN on
Motherboard Design Guide
Application Note
May 2007
317104-001
Revision 2.6

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Summary of Contents for Intel 82563EB

  • Page 1 82563EB/82564EB LAN on Motherboard Design Guide Application Note May 2007 317104-001 Revision 2.6...
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548- 4725 or by visiting Intel's website at http://www.intel.com.
  • Page 3 82563EB/82564EB LAN on Motherboard Design Guide Revision History Revision Revision Date Description May 2007 • Updated Exposed Pad* landing pattern options. May 2006 • Initial public release. Nov 2005 • Intel confidential release. 1.75 July 2005 • Added a third magnetics module to Table 3.
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  • Page 5: Table Of Contents

    General Design Considerations for Ethernet Platform LAN Connect Devices ..7 3.1.1 Clock Source .................... 7 3.1.2 Integrated Magnetics Module for 1000 BASE-T........7 Designing with the 82563EB/82564EB Gigabit Ethernet Platform LAN Connect.. 9 3.2.1 Powering Down the 82563EB/ 82564EB Gigabit Ethernet Platform LAN Connect........9 3.2.2 Serial EEPROM for 82563EB/ 82564EB Gigabit Ethernet Platform LAN Connect Implementations ..9...
  • Page 6 7.1.12 Traces for Decoupling Capacitors ............31 7.1.13 Ground Planes Under a Magnetics Module (Copper-Based Gigabit designs)......32 7.1.14 Light Emitting Diodes for Designs Based on 82563EB/82564EB Device ........34 7.1.15 Thermal Design Considerations ............. 34 Physical Layer Conformance Testing ..............34 7.2.1 Conformance Tests for 10/100/1000 Mbps Designs ......
  • Page 7 General Placement Distances for 1000 BASE-T Designs........26 Trace Routing......................29 Ground Plane Separation..................32 Ideal Ground Split Implementation ..............33 82563EB/82564EB Silkscreen and Components Pad (Top View) ......38 82563EB/82564EB Solder Mask.................39 82563EB/82564EB Solder Paste ................39 82563EB/82564EB Landing Pattern A (Top View - Vias on the Outside of the Exposed Pad*)........40 Landing Pattern B (Top View - Vias on the Outside of the Exposed Pad*)..41...
  • Page 8 82563EB/82564EB LAN on Motherboard Design Guide Note: This page is intentionally left blank. viii...

  • Page 9: Introduction

    The device connects directly to the Intel® 631xESB/632xESB I/O Controller Hub using the serial Kumeran interface. The 82563EB/82564EB Gigabit Platform LAN Connect device is packaged in a 14 mm x 14 mm x 1.2 mm with 0.5 mm pitch leads, 100-pin TQFL with Exposed-Pad*. An Exposed-Pad* is a central pad on the bottom of the package that serves as a ground and thermal connection.

  • Page 10: Reference Documents

    Crystal Frequently Asked Questions. Fox Electronics. • Resonator Terminology and Formulas. Piezo Technology, Inc. Note: Intel documentation is subject to frequent revision. Verify with your local Intel sales office that you have the latest information before finalizing a design Product Codes...

  • Page 11: Kumeran Connection To 82563Eb/82564Eb Gigabit Platform Lan Connect

    TXA_PLUS SERN0 TXA_MINUS LINK_1 LINK_B SETP1 RXB_PLUS Port 1 Port B SETN1 RXB_MINUS SERP1 TXB_PLUS 631xESB/ SERN1 TXB_MINUS 82563EB 632xESB SER_CLK_IN PHY_CLK_OUT NOTE: 82564EB will only have Port 0 to Port A connections. Figure 1. 82563EB/82564EB Connection to the 631xESB/632xESB...

  • Page 12: Kumeran Reference Clock

    NOTE: Figure also reflects the same behavior in the single port 82564EB device. If the length of the Kumeran board traces are 15 inches or less, then the 82563EB/82564EB uses its 25 MHz crystal and internal PLL to provide a 62.5 MHz clock to the 631xESB/632xESB. If the...

  • Page 13: 631Xesb/632Xesb To 82563Eb/82564Eb Signals

    Kumeran interface. The PHY_PWR_GOOD signal indicates that stable power is available for all voltage rails that power the 82563EB/82564EB and that the device is ready to come out of an otherwise held reset. Typically, this connects to the system’s RSM_RST# signal.
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  • Page 15: Ethernet Component Design Guidelines

    3.1.1 Clock Source All designs require a 25 MHz clock source. The 82563EB/82564EB Gigabit Ethernet Platform LAN Connect uses the 25 MHz source to generate clocks up to 125 MHz and 1.25 GHz for the PHY circuits, and 1.25 GHz for the Kumeran interface. For optimum results with lowest cost, connect a 25 MHz parallel resonant crystal and appropriate load capacitors at the XTAL1 and XTAL2 leads.

  • Page 16: Third-Party Magnetics Modules

    82563EB/82564EB LAN on Motherboard Design Guide The steps involved in magnetics module qualification are similar to those for crystal qualification: 1. Verify that the vendor’s published specifications in the component datasheet meet or exceed the required IEEE specifications. 2. Independently measure the component’s electrical parameters on the test bench, checking samples from multiple lots.

  • Page 17: Designing With The 82563Eb/82564Eb Gigabit Ethernet Platform Lan Connect

    Powering Down the 82563EB/82564EB Gigabit Ethernet Platform LAN Connect The 82563EB/82564EB device has a signal named PHY_SLEEP that can be used as an alternative to an in-band event for powering down the Ethernet PHY functions driven only by the 631xESB/ 632xESB.

  • Page 18: Lvr Circuit For The 82563Eb (Dual Port)

    The design may require two external PNP transistors, one for 1.9V and the other for 1.2V generation, if both voltages are going to be regulated by the 82563EB/82564EB. The beta for the PNP transistors must be 100 or better. For the 82563EB only (not applicable to 82564EB single...

  • Page 19: 82563Eb Power Sequencing

    The 82563EB/82564EB core voltage (1.2V) cannot exceed the 3.3V supply by more than 0.5V at any time during the power up. The 82563EB core voltage (1.2V) can not exceed the 1.9V supply by more than 0.5V at any time during the power up. The core voltage is not required to begin ramping before the 3.3V or the 1.9V supply.

  • Page 20: 82563Eb/82564Eb Device Power Supply Filtering

    82563EB/82564EB LAN on Motherboard Design Guide The 82563EB/82564EB device has a PHY_PWR_GOOD input. Treat this signal as an external device reset which works in conjunction with the internal power-on reset circuitry. In the situation where a central power supply furnishes all the voltage sources, PHY_PWR_GOOD can possibly be tied to the platform’s RSM_RST#.

  • Page 21: Xor Testing

    A common board or system-level manufacturing test for proper electrical continuity between a silicon component and the board is some type of cascaded-XOR or NAND tree test. The 82563EB/ 82564EB implements an XOR tree spanning most I/O signals. The component XOR tree consists of a series of cascaded XOR logic gates, each stage feeding in the electrical value from a unique pin.

  • Page 22: Tested Pins Included In Xor Tree (33 Pins)

    82563EB/82564EB LAN on Motherboard Design Guide Note: Some of the pins that are inputs for the XOR test are listed as “may be left disconnected” in the pin descriptions. If XOR test is used, all inputs to the XOR tree must be connected.

  • Page 23: Frequency Control Device Design Considerations

    “Crystal Selection Parameters”. The Intel® Ethernet controllers also have bus clock input functionality, however a discussion of this feature is beyond the scope of this document, and will not be addressed. The chosen frequency control device vendor should be consulted early in the design cycle. Crystal and oscillator manufacturers familiar with networking equipment clock requirements may provide assistance in selecting an optimum, low-cost solution.

  • Page 24: Programmable Crystal Oscillators

    82563EB/82564EB LAN on Motherboard Design Guide For Intel® Ethernet controllers, it is acceptable to overdrive the internal inverter by connecting a 25 MHz external oscillator to the XTAL1 lead, leaving the XTAL2 lead unconnected. The oscillator should be specified to drive CMOS logic levels, and the clock trace to the device should be as short as possible.

  • Page 25: Crystal Selection Parameters

    82563EB/82564EB LAN on Motherboard Design Guide Crystal Selection Parameters All crystals used with Intel® Ethernet controllers are described as “AT-cut,” which refers to the angle at which the unit is sliced with respect to the long axis of the quartz stone. The following...

  • Page 26: Nominal Frequency

    82563EB/82564EB LAN on Motherboard Design Guide Nominal Frequency Intel® Ethernet controllers use a crystal frequency of 25.000 MHz. The 25 MHz input is used to generate a 125 MHz transmit clock for 100BASE-TX and 1000BASE-TX operation – 10 MHz and 20 MHz transmit clocks, for 10BASE-T operation.

  • Page 27: Load Capacitance

    The formula for crystal load capacitance is as follows: ⋅ C1 C2 ------------------------- stray where C1 = C2 = 27 pF (as suggested in most Intel reference designs) and C = allowance for additional capacitance in pads, traces and the chip carrier stray within the Ethernet device package An allowance of 3 pF to 7 pF accounts for lumped stray capacitance.

  • Page 28: Shunt Capacitance

    AT strips, rather than circular AT quartz blanks. Some crystal data sheets list crystals with a maximum drive level of 1 mW. However, Intel® Ethernet controllers drive crystals to a level less than the suggested 750 µW value. This parameter does not have much value for on-chip oscillator use.

  • Page 29: Reference Crystal Selection

    10/100 and 10/100/1000Base-T Ethernet LAN, the transmitter reference frequency must be precise within ±50 ppm. Intel® recommends customers to use a transmitter reference frequency that is accurate to within ±30 ppm to account for variations in crystal accuracy due to crystal manufacturing tolerance.
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  • Page 31: Oscillator Support

    82563EB/82564EB LAN on Motherboard Design Guide Oscillator Support The 82563EB/82564EB clock input circuit is optimized for use with an external crystal. However, an oscillator can also be used in place of the crystal with the proper design considerations: • The clock oscillator has an internal voltage regulator of 1.2 V to isolate it from the external noise of other circuits to minimize jitter.

  • Page 32: Oscillator Solution

    82563EB/82564EB LAN on Motherboard Design Guide Oscillator Solution There are two possible oscillator solutions: high voltage and low voltage. 6.1.1 High Voltage Solution (VDD = 3.3V) This solution involves capacitor C1, which forms a capacitor divider with C of about 20 pF.

  • Page 33: Ethernet Component Layout Guidelines

    Designing for 1000 BASE-T Gigabit operation is very similar to designing for 10 and 100 Mbps. For the 82563EB/82564EB Gigabit Ethernet Platform LAN Connect, system level tests should be performed at all three speeds.

  • Page 34: Crystals And Oscillators

    0.75 of an inch. Ensure that the traces from XTAL1 and XTAL2 on the 82563EB/82564EB are routed symmetrically their lengths are matched. If an oscillator is used instead, connect the clock signal with the shortest, most direct trace possible.

  • Page 35: Board Stack Up Recommendations

    82563EB/82564EB LAN on Motherboard Design Guide 7.1.3 Board Stack Up Recommendations Printed circuit boards for these designs typically have six or more layers. Although, the 82563EB/ 82564EB does not dictate the stackup, here is an example of a typical six-layer board stackup: •...

  • Page 36: Trace Length And Symmetry For 1000 Base-T Designs

    82563EB/82564EB LAN on Motherboard Design Guide Each pair of signal should have a differential impedance of 100 Ω. +/- 20%. If a particular tool cannot design differential traces, it is permissible to specify 55-65 Ω single-ended traces as long as the spacing between the two traces is minimized.

  • Page 37: Signal Termination And Coupling

    82563EB/82564EB LAN on Motherboard Design Guide • Keep maximum separation within differential pairs to 9 mils. • For high-speed signals, the number of corners and vias should be kept to a minimum. If a 90° bend is required, it is recommended to use two 45° bends instead. Refer to Figure •...

  • Page 38: Impedance Discontinuities

    82563EB/82564EB LAN on Motherboard Design Guide 7.1.8 Impedance Discontinuities Impedance discontinuities cause unwanted signal reflections. Minimize vias (signal through holes) and other transmission line irregularities. If vias must be used, a reasonable budget is two per differential trace. Unused pads and stub traces should also be avoided.

  • Page 39: Traces For Decoupling Capacitors

    82563EB/82564EB LAN on Motherboard Design Guide The following guidelines help reduce circuit inductance in both backplanes and motherboards: • Route traces over a continuous plane with no interruptions. Do not route over a split power or ground plane. If there are vacant areas on a ground or power plane, avoid routing signals over the vacant area.

  • Page 40: Ground Planes Under A Magnetics Module (Copper-Based Gigabit Designs)

    82563EB/82564EB LAN on Motherboard Design Guide 7.1.13 Ground Planes Under a Magnetics Module (Copper-Based Gigabit designs) The magnetics module chassis or output ground (secondary side of transformer) should be separated from the digital or input ground (primary side) by a physical separation of 100 mils minimum.

  • Page 41: Ideal Ground Split Implementation

    82563EB/82564EB LAN on Motherboard Design Guide filter high frequency emissions. The value(s) of the capacitor stuffing options may be different for each board. Experiments will need to be performed to determine which value(s) provide best EMI performance. Board Edge RJ/Mag.

  • Page 42: Light Emitting Diodes For Designs Based On 82563Eb/82564Eb Device

    Light Emitting Diodes for Designs Based on 82563EB/82564EB Device The 82563EB/82564EB device provides seven total LEDs for each port. Four primary LEDs are programmable by the MAC in the 631xESB/632xESB enabling 16 different possible modes that are set in the EEPROM. Three LEDs are fixed and non-programmable. Of the three secondary LEDs, one is used for IEEE debug test header;...

  • Page 43: Conformance Tests For 10/100/1000 Mbps Designs

    82563EB/82564EB LAN on Motherboard Design Guide 7.2.1 Conformance Tests for 10/100/1000 Mbps Designs Crucial tests are as follows, listed in priority order: • Bit Error Rate (BER). Good indicator of real world network performance. Perform bit error rate testing with long and short cables and many link partners. The test limit is 10 errors.
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  • Page 45: 82563Eb/82564Eb Exposed Pad

    82563EB/82564EB Exposed Pad* Introduction The 82563EB/82564EB is a 100-pin, 14 mm x 14 mm TQFP package with an Exposed-Pad*. The Exposed-Pad* is a central pad on the bottom of the package that provides the primary heat removal path as well as electrical grounding for a Printed Circuit Board (PCB).

  • Page 46: Component Pad, Solder Mask And Solder Paste

    82563EB/82564EB LAN on Motherboard Design Guide Component Pad, Solder Mask and Solder Paste Figure Figure 15, and Figure 16 shows the silkscreen/components pad, solder mask and solder paste area for the 82563EB/82564EB package. Figure 14. 82563EB/82564EB Silkscreen and Components Pad (Top View)

  • Page 47: 82563Eb/82564Eb Solder Mask

    82563EB/82564EB LAN on Motherboard Design Guide Figure 15. 82563EB/82564EB Solder Mask 0.12 in. 0.30 mm 0.12 in. 0.30 mm 0.054 in. (1.38 mm) Square x 9 Figure 16. 82563EB/82564EB Solder Paste The stencil for the solder paste should be 5 mils thick. Also, use a solder paste alloy consisting of...

  • Page 48: Landing Pattern A (No Via In Pad)

    Extended Ground Connection Without Thermal Relief Metal Pattern Solder Mask Opening Figure 17. 82563EB/82564EB Landing Pattern A (Top View - Vias on the Outside of the Exposed Pad*) Use 12 vias distributed on four sides (three per side, as shown in Figure 17) or three sides (four per side).

  • Page 49: Landing Pattern B (Thermal Relief; No Via In Pad)

    Landing Pattern B (Thermal Relief; No Via In Pad) This landing pattern (vias outside Exposed Pad*) provides better solder coverage and less voiding than landing pattern C (vias inside Exposed Pad*). This landing pattern also meets Intel’s recommendation for coverage >= 80%.

  • Page 50: Landing Pattern C (Via In Pad)

    36 mil anti-pad 20 mil via pad 82 mil closed via in Exposed Pad* 82 mil Exposed Pad* Figure 19. 82563EB/82564EB Landing Pattern C (Top View - Vias on the Inside of the Exposed Pad*)

  • Page 51: Bill Of Materials (Bom)

    82563EB/82564EB LAN on Motherboard Design Guide Bill of Materials (BOM) Table 13. BOM for the 631xESB/632xESB and the 82563EB/82564EB Gigabit Platform LAN Connect Device Component Notes 631xESB/ Does not Include Management Interface 632xESB 24.9 Ω , 1% Tolerance SEICOMP Resistor 10 K Ω...
  • Page 52 82563EB/82564EB LAN on Motherboard Design Guide Device Component Notes 82563EB/ 82564EB 0.1 µ F, X7R, 10V, 0603 Kumeran AC Coupling 4.7 K Ω , 5% Strappings 4.99 K Ω , 1% BIAS Resistor 1 K Ω , 5% Strappings 25.000 MHz, +/- 30 ppm Crystal...

  • Page 53: Design, Layout, And Test Checklists

    10.0 Design, Layout, and Test Checklists Design, Layout and Test checklists for the 82563EB/82564EB Gigabit Ethernet Platform LAN Connect are available to aid designers. These schematics are also available in spreadsheet format on the Intel public web site at: www.intel.com/developer.
  • Page 54 20 pF. Specify Equivalent Series Resistance (ESR) to be 50 Ω or less. If using an oscillator instead, contact Intel for important circuit modifications. Avoid PLL clock buffers. Connect two load caps to crystal; one on XTAL1 Capacitance affects accuracy of the frequency.
  • Page 55 Connect TEST_JTAG to VCCAUX3_3 with a 1 to 10 K Ω resistor. Connect MDIO_ADD[3:0] to GND with a 1 to The MDIO interface is not used on the 82563EB/ 10 K Ω resistor. 82564EB. Connect MDC to GND with a 1 K to 10 K Ω...
  • Page 56 Place two 1.0 Ω , 0.25 W, 5% resistors in parallel Resistors are required when used with the in the collector path of the PNP transistors. 82563EB. The resistors must be in the collector path, not the emitter path for the regulator to operate without oscillations.
  • Page 57 GND. For production applications, all test points may be deleted and signal pins may be left unconnected. Mfg Test 82563EB device uses a 3.3V JTAG Test Access The TAP controller uses internal reset instead of Port. an external pin.

  • Page 58: Board Layout And Placement Checklist

    82563EB/82564EB LAN on Motherboard Design Guide 10.2 Board Layout and Placement Checklist SECTION CHECK ITEMS REMARKS General Have up-to-date product documentation and Documents are subject to frequent change. spec updates. Route the Kumeran and MDI differential traces Layout of differential traces is critical.
  • Page 59 82563EB/82564EB LAN on Motherboard Design Guide SECTION CHECK ITEMS REMARKS MDI Differential Avoid highly resistive traces, for example, 4 mil If trace length is a problem, use thicker board Pairs traces longer than 4 inches. dielectrics to allow wider traces. Thicker copper is even better than wider traces.
  • Page 60 82563EB/82564EB LAN on Motherboard Design Guide SECTION CHECK ITEMS REMARKS Kumeran For differential traces that will be longer than 15 Transmit and inches, the dielectric height under microstrip traces Receive and the dielectric heights above/below stripline Interface traces should be >= 4.3 mils nominal. For long...
  • Page 61 82563EB/82564EB LAN on Motherboard Design Guide SECTION CHECK ITEMS REMARKS Kumeran Make sure digital signals on adjacent layers cross Transmit and at 90° angles. Receive Interface For the Kumeran interface, place AC coupling The AC coupling is always at the receiver on the capacitors close to the receivers.

  • Page 62: Validation Checklist

    SECTION CHECK ITEMS REMARKS Landing Pattern Make sure that the 82563EB/82564EB has a Check for solder voids on the Exposed-Pad,* good connection to ground. solder wicking, or a complete lack of solder. Failure to ensure a good connection to ground might cause link-up problems.

  • Page 63: Reference Schematic

    82563EB/82564EB LAN on Motherboard Design Guide 11.0 Reference Schematic Reference schematics describing a typical design layout for the 82563EB/82564EB Gigabit Ethernet Platform LAN Connect can be found in the Bensley/Bensley-VS Platform Design Guide (PDG).
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  • Page 65: System Manageability

    82563EB/82564EB LAN on Motherboard Design Guide 12.0 System Manageability Refer to the 82571/82572/631xESB/632xESB System Manageability Application Note (AP-497) for information about the pass through modes that enable an external Baseboard Management Controller (BMC) or TCO controller to communicate with 631xESB/632xESB I/O Controller Hub using a TCO port.
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  • Page 67: Measuring Lan Reference Frequency Using A Frequency Counter

    ±50 parts per million (ppm). Note: Intel recommends a frequency tolerance of ±30 (ppm). Most Intel LAN devices will operate properly with a 25.000 MHz reference crystal, provided it meets the recommended requirements for frequency stability, equivalent series resistance at resonance (ESR), and load capacitance.

  • Page 68: Indirect Frequency Measurement And Frequency Accuracy Calculation Steps

    82563EB/82564EB LAN on Motherboard Design Guide Almost all Intel LAN silicon that support 1000BASE-T Ethernet can provide a buffered 125 MHz clock, which can be used for indirect probing of the transmitter reference clock. The buffered 125 MHz clock will be a 5X multiple of the crystal circuit’s reference frequency (Figure 20).

  • Page 69: Direct Probing Test Method, Applicable For Most 10/100 Devices (Devices That Do Not Support 1000Base-T)

    82563EB/82564EB LAN on Motherboard Design Guide – FrequencyAccuracy ppm ------------------------------- - ⁄ y 1000000 where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 1. Given: The measured averaged center frequency is 124.99942 MHz (or 124,999,420 Hertz).

  • Page 70: Direct Frequency Measurement And Frequency Accuracy Calculation Steps

    82563EB/82564EB LAN on Motherboard Design Guide The probe should be connected between the XTAL2 pin of the LAN device and a nearby ground. Typically, it is possible to connect the probe pins across one of the discrete load capacitors (C2 in Figure 21).
  • Page 71 82563EB/82564EB LAN on Motherboard Design Guide – FrequencyAccuracy ppm ------------------------------- - ⁄ y 1000000 where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 1. Given: The measured averaged center frequency is 24.99963 MHz (or 24,999,630 Hertz).
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