Figure 84. Trace Routing - Intel 815EG Design Manual

R

Figure 84. Trace Routing

Trace
11.9.2.1.1 Trace Geometry and Length
The key factors in controlling trace EMI radiation are the trace length and the ratio of trace width
to trace height above the ground plane. To minimize trace inductance, high-speed signals and
signal layers close to a ground or power plane should be as short and wide as practical. Ideally,
this ratio of trace width to height above the ground plane is between 1:1 and 3:1. To maintain trace
impedance, the width of the trace should be modified when changing from one board layer to
another, if the two layers are not equidistant from the power or ground plane. Differential trace
impedances should be controlled to ~100 Ω. It is necessary to compensate for trace-to-trace edge
coupling, which can lower the differential impedance by 10 Ω, when the traces within a pair are
closer than 0.030 inch (edge to edge).
Traces between decoupling and I/O filter capacitors should be as short and wide as practical.
Long-and-thin traces are more inductive and would reduce the intended effect of the decoupling
capacitors. For similar reasons, traces to I/O signals and signal terminations should be as short as
possible. Vias to the decoupling capacitors should have diameters sufficiently large to decrease
series inductance. Additionally, the PLC should not be closer than one inch to the
connector/magnetics/edge of the board.
11.9.2.1.2 Signal Isolation
Comply with the following rules for signal isolation:
• Separate and group signals by function on separate layers if possible. Maintain a gap of
100 mils between all differential pairs (Phoneline and Ethernet) and other nets, but group
associated differential pairs together.
®
Intel 815EG Chipset Platform Design Guide
45
degrees
45 degrees
I/O Subsystem
137