Power Management; Figure 103. Usb Data Line Schematic - Intel 815EG Design Manual

R

Figure 103. USB Data Line Schematic

Driver
P+
Driver
P-
ICH2
14.4.9

Power Management

Checklist Items
THRM#
SLP_S3#
SLP_S5#
PWROK
PWRBTN#
RI#
RSMRST#
®
Intel 815EG Chipset Platform Design Guide
Motherboard trace
15 Ω
< 1"
45 Ω
15 kΩ
Optional
Motherboard trace
15 Ω
< 1"
45 Ω
15 kΩ
Optional
Transmission line
• Connect to temperature Sensor. Pull-up if not used.
• No pull-up/down resistors needed. Signals driven by ICH2.
• This signal should be connected to power monitoring logic, and should go high
no sooner than 10 ms after both VCC3_3 and VCC1_8 have reached their
nominal voltages. For systems implementing the universal PGA370 design, this
signal must be connected to the gating circuit found in Section 4.3.2.
• No extra pull-up resistors. This signal has an integrated pull-up of 24 k Ω.
• RI# does not have an internal pull-up. Recommend an 8.2 k Ω pull-up resistor to
Resume well
• If this signal is enabled as a wake event, it is important to keep this signal
powered during the power loss event. If this signal goes low (active), when
power returns the RI_STS bit will be set and the system will interpret that as a
wake event.
• Connect to power monitoring logic, and should go high no sooner than 10 ms
after both VCCSus3_3 and VCCSus1_8 have reached their nominal voltages.
Requires weak pull-down. Also requires well isolation control as directed in
Section 11.8.6.
System Design Checklist
47 pf
47 pf
USB twisted-pair cable
Recommendations
90 Ω
usb_data_line_schem
183