Ich2; Figure 23 Pwrok Gating Circuit For Intel ® Ich2 - Intel 815EG Design Manual

Universal Socket 370 Design
4.3.2 Gating of PWROK to Intel
With power being gated to the CK-815 by the signal VTTPWRGD12, it is important that the
clocks to the ICH2 are stable before the power supply asserts PWROK to the ICH2. As the
clocking power gating circuitry relies on the 12-V supply, there is no guarantee that these
conditions will be met. This is why an estimated minimum time delay of 20 ms must be added after
power is connected to the CK-815 to give the clock driver sufficient time to stabilize. This time
delay will gate the power supply's assertion of PWROK to the ICH2. After the time delay, the
power supply can safely assert PWROK to the ICH2, with the ICH2 subsequently taking the
GMCH out of reset. Refer to Figure 23 for an example implementation.
Figure 23 PWROK Gating Circuit for Intel
NOTES: The diode is included so that repeated pressing of the reset or power button does not cause the
capacitor to build up enough charge to circumvent the 20 ms delay.
48
®

ICH2

VDD on CK-815 VCC3_3
43k
1.0uF PWROK
®
ICH2
Note: delay 20ms after
VDD on CK-815 is
powered
ICH2_PWROK_GATING
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Intel 815EG Chipset Platform Design Guide
R
ICH2_PWROK