Xilinx SP605 Hardware User's Manual page 14

Chapter 1: SP605 Evaluation Board
Table 1-1: SP605 Features (Cont'd)
14
Number Feature
Clock Generation
a. 200 MHz oscillator
7
b. Oscillator socket, single-
ended, LVCMOS
c. SMA connectors
GTP port SMA x4 and
8
MGT Clocking SMA (REFCLK)
9 PCIe 1-lane edge conn.(Gen 1)
10 SFP Module Cage/Connector
11 Ethernet 10/100/1000
12 USB JTAG Conn. (USB Mini-B)
13 DVI Codec and Video Connector
14 IIC EEPROM (on backside)
Status LEDs
a. FMC Power Good
b. System ACE CF Status
c. FPGA INIT and DONE
15
d. Ethernet PHY Status
e. JTAG USB Status
f. FPGA Awake
g. TI Power Good
h. MGT AVCC, DDR3 Term
Pwr Good
a. User LEDs (4)
b. User Pushbuttons (4)
16
c. User DIP Switch (4-pole)
d. User SMA (2)
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Notes
200 MHz OSC, oscillator socket,
SMA connectors
SiTime 200 MHz 2.5V LVDS
MMD Components 2.5V 27 MHz
SMA pair P(J41) / N(J38)
MGT RX,TX Pairs x4 SMA MGT
REFCLK x2 SMA
Card Edge Connector, 1-lane
AMP 136073-1
Marvell M88E1111 EPHY
USB JTAG Download Circuit
Chrontel CH7301C-TF
ST Micro M24C08-WDW6TP
Red LEDs (active-High)
Active-High
4-pole (active-High)
GPIO x2 SMA
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
Schematic
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