Xilinx SP605 Hardware User's Manual page 17

Table 1-3: Termination Resistor Requirements (Cont'd)
Notes:
1. Nominal value of V
Table 1-4: FPGA On-Chip (OCT) Termination External Resistor Requirements
Table 1-5
Table 1-5: DDR3 Component Memory Connections
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
Signal Name
MEM1_ODT
MEM1_DQ[15:0]
MEM1_UDQS[P,N], MEM1_LDQS[P,N]
MEM1_UDM, MEM1_LDM
MEM1_CK[P,N]
for DDR3 interface is 0.75V.
TT
U1 FPGA Pin
ZIO
RZQ
shows the connections and pin numbers for the DDR3 Component Memory.
U1 FPGA
Schematic Net Name
Pin
K2 MEM1_A0
K1 MEM1_A1
K5 MEM1_A2
M6 MEM1_A3
H3 MEM1_A4
M3 MEM1_A5
L4 MEM1_A6
K6 MEM1_A7
G3 MEM1_A8
G1 MEM1_A9
J4 MEM1_A10
E1 MEM1_A11
F1 MEM1_A12
J6 MEM1_A13
H5 MEM1_A14
J3 MEM1_BA0
J1 MEM1_BA1
H1 MEM1_BA2
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Board Termination
4.7 KΩ to GND
–
–
–
100Ω differential at memory
component
FPGA Pin Number Board Connection for OCT
M7
K7
Memory U42
Pin Number
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M2
N8
M3
Detailed Description
On-Die Termination
–
ODT
ODT
ODT
–
No Connect
100Ω to GROUND
Pin Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCN
NC/A13
NC/A14
BA0
BA1
BA2
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