User Sip Header - Xilinx SP605 Hardware User's Manual

User SIP Header

The SP605 includes a 6-pin single-inline (SIP) male pin header (J55) for FPGA GPIO access.
Four pins of J55 are wired to the FPGA through 200Ω series resistors and a level shifter, and
the remaining two J55 pins are wired to 3.3V and GND. The J55 header is described in
Figure 1-18
X-Ref Target - Figure 1-18
VCC1V5_FPGA
U1 FPGA Pin
GPIO_HEADER_0_LS
G7
GPIO_HEADER_1_LS
H6
GPIO_HEADER_2_LS
D1
GPIO_HEADER_3_LS
R7
NC
NC
NC
NC
Table 1-26: User SIP Header Connections
Notes:
1. Each GPIO_HEADER_n signal is sourced from the FPGA as
2. Each GPIO_HEADER_n net has a 200Ω series resistor between the
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
and Table 1-26.
VCC3V3
U52
2 19
VCCA VCCB
1 20
A1 B1
3 18
A2 B2
4 17
A3 B3
5 16
A4 B4
6 15
A5 B5
7 14
A6 B6
8 13
A7 B7
9 12
A8 B8
10 11
OE GND
TXB0108
1
2
Figure 1-18: User SIP Header J55
U1 FPGA Pin Schematic Net Name GPIO Header Pin
G7 GPIO_HEADER_0
H6 GPIO_HEADER_1
D1 GPIO_HEADER_2
R7 GPIO_HEADER_3
–
– VCC3V3
<netname>_LS to a level shifter, then to the J55 header.
level shifter and its respective header pin.
www.xilinx.com
GPIO_HEADER_0
GPIO_HEADER_0
GPIO_HEADER_1
GPIO_HEADER_1
GPIO_HEADER_2
GPIO_HEADER_3
GPIO_HEADER_2
NC
NC
GPIO_HEADER_3
NC
NC
C384
X5R
10V
0.1UF
J55.1
J55.2
J55.3
J55.4
GND J55.5
J55.6
Detailed Description
HDR_1x6
J55
1
2
3
4
5
6
DNP
VCC3V3
UG526_18 _092409
47