Spi X4 Flash - Xilinx SP605 Hardware User's Manual

See the Micron Technology, Inc. DDR3 SDRAM Specification for more information.
Also, see the Spartan-6 FPGA Memory Controller User Guide (UG388).

3. SPI x4 Flash

The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT
configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are
3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash
through a 2.5V bank. The XC6SLX45T-3FGG484 is a master device when accessing an
external SPI flash memory device.
The SP605 SPI interface has two parallel connected configuration options
SPI X4 (Winbond W25Q64FVSFIG) 64-Mb flash memory device (U32) and a flash
programming header (J17). J17 supports a user-defined SPI mezzanine board. The SPI
configuration source is selected via SPI select jumper J46. For details on configuring the
FPGA, see
X-Ref Target - Figure 1-3
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
Configuration Options.
SPI Prog
J17
TMS
TDI
TDO
Silkscreen
TCK
GND
3V3
HDR_1X9
Figure 1-3: J17 SPI Flash Programming Header
www.xilinx.com
FPGA_PROG_B
1
FPGA_D2_MISO3
2
3 FPGA_D1_MISO2
SPI_CS_B
4
FPGA_MOSI_CSI_B_MISO0
5
FPGA_D0_DIN_MISO_MISO1
6
FPGA_CCLK
7
GND
8
VCC3V3
9
UG526_03_092409
Detailed Description
[Ref 15]
[Ref 3]
(Figure 1-3): an
19