Xilinx SP605 Hardware User's Manual page 3

Date Version
07/18/11 1.6
06/19/12 1.7
09/24/12 1.8
02/14/19 1.9
UG526 (v1.9) February 14, 2019
Corrected "jitter" to "stability" in section
and notes descriptions for reference numbers
numbers for ZIO and RZQ
Table 1-30.
Removed reference to FPGA speed grade in
Added IIC External Access
designator in 8. Multi-Gigabit Transceivers (GTP
Updated Figure 1-2. Added
Updated the Electrostatic Discharge Caution
Constraints, and Appendix D, Regulatory and Compliance
MB DDR3 Component Memory.
www.xilinx.com
Revision
Oscillator (Differential). Revised the feature
6 and 12
in Table 1-4. Added Table
2. 128 MB DDR3 Component
Header. Updated SFP Module connector reference
MGTs).
Regulatory and Compliance
section,
in Table 1-1. Revised FPGA pin
1-29, Table 1-31, and table notes in
Memory.
Information.
Appendix C, Xilinx Design
Information. Updated
SP605 Hardware User Guide
2. 128